1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Rockchip Electronics Co., Ltd.
4 *
5 * Author: Huang Lee <Putin.li@rock-chips.com>
6 */
7
8 #define pr_fmt(fmt) "rga2_reg: " fmt
9
10 #include "rga_job.h"
11 #include "rga2_reg_info.h"
12 #include "rga2_mmu_info.h"
13 #include "rga_hw_config.h"
14
15 extern struct rga2_mmu_info_t rga2_mmu_info;
16
17 unsigned int rga2_rop_code[256] = {
18 0x00000007, 0x00000451, 0x00006051, 0x00800051,
19 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
20 0x00800765, 0x000004b0, 0x00000065, 0x000004f4,
21 0x00000075, 0x000004e6, 0x00804850, 0x00800005,
22
23 0x00006850, 0x00800050, 0x00805028, 0x00000568,
24 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1
25 0x008007aa, 0x00036071, 0x00002c6a, 0x00803631,
26 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,
27
28 0x0080066e, 0x00000528, 0x00000066, 0x0000056c,
29 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2
30 0x00800631, 0x0002b471, 0x00006071, 0x008037aa,
31 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,
32
33 0x0000006e, 0x00000565, 0x00003451, 0x00800006,
34 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3
35 0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c,
36 0x00000031, 0x00834850, 0x000034e6, 0x00800071,
37
38 0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870,
39 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4
40 0x00800728, 0x0002a561, 0x000026c2, 0x008002c6,
41 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,
42
43 0x0000006c, 0x00000475, 0x000024e2, 0x008036b0,
44 0x00804051, 0x00800004, 0x00800251, 0x00000651,
45 0x00002e4a, 0x0080024e, 0x00000028, 0x00824842,
46 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5
47
48 0x008006b0, 0x000234f0, 0x00002741, 0x00800345,
49 0x00003651, 0x00800255, 0x00000030, 0x00834051,
50 0x00a34842, 0x000002b0, 0x00800271, 0x0002b651,
51 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6
52
53 0x00006870, 0x008037a2, 0x00003431, 0x00000745,
54 0x00002521, 0x00000655, 0x0000346e, 0x00800062,
55 0x008002f0, 0x000236d0, 0x000026d4, 0x00807028,
56 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7
57
58 0x00800671, 0x000005aa, 0x00006031, 0x008036c6,
59 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,
60 0x00000070, 0x0080346e, 0x00800655, 0x00802521,
61 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8
62
63 0x00006830, 0x0080364e, 0x00822f48, 0x00000361,
64 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,
65 0x00034051, 0x00800030, 0x0080026e, 0x00803651,
66 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9
67
68 0x00000068, 0x00802c75, 0x0080064e, 0x008024a2,
69 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,
70 0x00800651, 0x00000251, 0x00800000, 0x00004051,
71 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a
72
73 0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068,
74 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,
75 0x00002f28, 0x00802561, 0x0080046e, 0x00000046,
76 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b
77
78 0x00000071, 0x008034e6, 0x00034850, 0x00800031,
79 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,
80 0x00800748, 0x00000341, 0x000026a2, 0x008034f0,
81 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c
82
83 0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0,
84 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,
85 0x00002e2a, 0x00803471, 0x00826862, 0x010007aa,
86 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d
87
88 0x008006d0, 0x000002d0, 0x00002721, 0x00802d68,
89 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,
90 0x010037aa, 0x00a36870, 0x00800471, 0x00004031,
91 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e
92
93 0x00800001, 0x00004850, 0x008004e6, 0x0000004e,
94 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,
95 0x008004f0, 0x00004830, 0x00000048, 0x0080044e,
96 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
97 };
98
RGA2_reg_get_param(unsigned char * base,struct rga2_req * msg)99 static void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
100 {
101 u32 *bRGA_SRC_X_FACTOR;
102 u32 *bRGA_SRC_Y_FACTOR;
103 u32 sw, sh;
104 u32 dw, dh;
105 u32 param_x, param_y;
106
107 bRGA_SRC_X_FACTOR = (u32 *) (base + RGA2_SRC_X_FACTOR_OFFSET);
108 bRGA_SRC_Y_FACTOR = (u32 *) (base + RGA2_SRC_Y_FACTOR_OFFSET);
109
110 if (((msg->rotate_mode & 0x3) == 1) ||
111 ((msg->rotate_mode & 0x3) == 3)) {
112 dw = msg->dst.act_h;
113 dh = msg->dst.act_w;
114 } else {
115 dw = msg->dst.act_w;
116 dh = msg->dst.act_h;
117 }
118
119 sw = msg->src.act_w;
120 sh = msg->src.act_h;
121
122 if (sw > dw) {
123 #if SCALE_DOWN_LARGE
124 param_x = ((dw) << 16) / (sw) + 1;
125 #else
126 param_x = ((dw) << 16) / (sw);
127 #endif
128 *bRGA_SRC_X_FACTOR |= ((param_x & 0xffff) << 0);
129 } else if (sw < dw) {
130 #if SCALE_UP_LARGE
131 param_x = ((sw - 1) << 16) / (dw - 1);
132 #else
133 param_x = ((sw) << 16) / (dw);
134 #endif
135 *bRGA_SRC_X_FACTOR |= ((param_x & 0xffff) << 16);
136 } else {
137 *bRGA_SRC_X_FACTOR = 0; //((1 << 14) << 16) | (1 << 14);
138 }
139
140 if (sh > dh) {
141 #if SCALE_DOWN_LARGE
142 param_y = ((dh) << 16) / (sh) + 1;
143 #else
144 param_y = ((dh) << 16) / (sh);
145 #endif
146 *bRGA_SRC_Y_FACTOR |= ((param_y & 0xffff) << 0);
147 } else if (sh < dh) {
148 #if SCALE_UP_LARGE
149 param_y = ((sh - 1) << 16) / (dh - 1);
150 #else
151 param_y = ((sh) << 16) / (dh);
152 #endif
153 *bRGA_SRC_Y_FACTOR |= ((param_y & 0xffff) << 16);
154 } else {
155 *bRGA_SRC_Y_FACTOR = 0; //((1 << 14) << 16) | (1 << 14);
156 }
157 }
158
RGA2_set_mode_ctrl(u8 * base,struct rga2_req * msg)159 static void RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)
160 {
161 u32 *bRGA_MODE_CTL;
162 u32 reg = 0;
163 u32 render_mode = msg->render_mode;
164
165 bRGA_MODE_CTL = (u32 *) (base + RGA2_MODE_CTRL_OFFSET);
166
167 if (msg->render_mode == 4)
168 render_mode = 3;
169
170 reg =
171 ((reg & (~m_RGA2_MODE_CTRL_SW_RENDER_MODE)) |
172 (s_RGA2_MODE_CTRL_SW_RENDER_MODE(render_mode)));
173 reg =
174 ((reg & (~m_RGA2_MODE_CTRL_SW_BITBLT_MODE)) |
175 (s_RGA2_MODE_CTRL_SW_BITBLT_MODE(msg->bitblt_mode)));
176 reg =
177 ((reg & (~m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT)) |
178 (s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(msg->color_fill_mode)));
179 reg =
180 ((reg & (~m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET)) |
181 (s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(msg->alpha_zero_key)));
182 reg =
183 ((reg & (~m_RGA2_MODE_CTRL_SW_GRADIENT_SAT)) |
184 (s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(msg->alpha_rop_flag >> 7)));
185 reg =
186 ((reg & (~m_RGA2_MODE_CTRL_SW_INTR_CF_E)) |
187 (s_RGA2_MODE_CTRL_SW_INTR_CF_E(msg->CMD_fin_int_enable)));
188
189 *bRGA_MODE_CTL = reg;
190 }
191
RGA2_set_reg_src_info(u8 * base,struct rga2_req * msg)192 static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg)
193 {
194 u32 *bRGA_SRC_INFO;
195 u32 *bRGA_SRC_BASE0, *bRGA_SRC_BASE1, *bRGA_SRC_BASE2;
196 u32 *bRGA_SRC_VIR_INFO;
197 u32 *bRGA_SRC_ACT_INFO;
198 u32 *bRGA_MASK_ADDR;
199 u32 *bRGA_SRC_TR_COLOR0, *bRGA_SRC_TR_COLOR1;
200
201 u8 src_fmt_yuv400_en = 0;
202
203 u32 reg = 0;
204 u8 src0_format = 0;
205
206 u8 src0_rb_swp = 0;
207 u8 src0_alpha_swp = 0;
208
209 u8 src0_cbcr_swp = 0;
210 u8 pixel_width = 1;
211 u32 stride = 0;
212 u32 uv_stride = 0;
213 u32 mask_stride = 0;
214 u32 ydiv = 1, xdiv = 2;
215 u8 yuv10 = 0;
216
217 u32 sw, sh;
218 u32 dw, dh;
219 u8 rotate_mode;
220 u8 scale_w_flag, scale_h_flag;
221
222 bRGA_SRC_INFO = (u32 *) (base + RGA2_SRC_INFO_OFFSET);
223
224 bRGA_SRC_BASE0 = (u32 *) (base + RGA2_SRC_BASE0_OFFSET);
225 bRGA_SRC_BASE1 = (u32 *) (base + RGA2_SRC_BASE1_OFFSET);
226 bRGA_SRC_BASE2 = (u32 *) (base + RGA2_SRC_BASE2_OFFSET);
227
228 bRGA_SRC_VIR_INFO = (u32 *) (base + RGA2_SRC_VIR_INFO_OFFSET);
229 bRGA_SRC_ACT_INFO = (u32 *) (base + RGA2_SRC_ACT_INFO_OFFSET);
230
231 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
232
233 bRGA_SRC_TR_COLOR0 = (u32 *) (base + RGA2_SRC_TR_COLOR0_OFFSET);
234 bRGA_SRC_TR_COLOR1 = (u32 *) (base + RGA2_SRC_TR_COLOR1_OFFSET);
235
236 if (msg->src.format == RGA2_FORMAT_YCbCr_420_SP_10B ||
237 msg->src.format == RGA2_FORMAT_YCrCb_420_SP_10B) {
238 if ((msg->src.act_w == msg->dst.act_w) &&
239 (msg->src.act_h == msg->dst.act_h) &&
240 (msg->rotate_mode == 0))
241 msg->rotate_mode = 1 << 6;
242 }
243
244 {
245 rotate_mode = msg->rotate_mode & 0x3;
246
247 sw = msg->src.act_w;
248 sh = msg->src.act_h;
249
250 if ((rotate_mode == 1) | (rotate_mode == 3)) {
251 dw = msg->dst.act_h;
252 dh = msg->dst.act_w;
253 } else {
254 dw = msg->dst.act_w;
255 dh = msg->dst.act_h;
256 }
257
258 if (sw > dw)
259 scale_w_flag = 1;
260 else if (sw < dw)
261 scale_w_flag = 2;
262 else {
263 scale_w_flag = 0;
264 if (msg->rotate_mode >> 6)
265 scale_w_flag = 3;
266 }
267
268 if (sh > dh)
269 scale_h_flag = 1;
270 else if (sh < dh)
271 scale_h_flag = 2;
272 else {
273 scale_h_flag = 0;
274 if (msg->rotate_mode >> 6)
275 scale_h_flag = 3;
276 }
277 }
278
279 switch (msg->src.format) {
280 case RGA2_FORMAT_RGBA_8888:
281 src0_format = 0x0;
282 pixel_width = 4;
283 break;
284 case RGA2_FORMAT_BGRA_8888:
285 src0_format = 0x0;
286 src0_rb_swp = 0x1;
287 pixel_width = 4;
288 break;
289 case RGA2_FORMAT_RGBX_8888:
290 src0_format = 0x1;
291 pixel_width = 4;
292 msg->src_trans_mode &= 0x07;
293 break;
294 case RGA2_FORMAT_BGRX_8888:
295 src0_format = 0x1;
296 src0_rb_swp = 0x1;
297 pixel_width = 4;
298 msg->src_trans_mode &= 0x07;
299 break;
300 case RGA2_FORMAT_RGB_888:
301 src0_format = 0x2;
302 pixel_width = 3;
303 msg->src_trans_mode &= 0x07;
304 break;
305 case RGA2_FORMAT_BGR_888:
306 src0_format = 0x2;
307 src0_rb_swp = 1;
308 pixel_width = 3;
309 msg->src_trans_mode &= 0x07;
310 break;
311 case RGA2_FORMAT_RGB_565:
312 src0_format = 0x4;
313 pixel_width = 2;
314 msg->src_trans_mode &= 0x07;
315 break;
316 case RGA2_FORMAT_RGBA_5551:
317 src0_format = 0x5;
318 pixel_width = 2;
319 break;
320 case RGA2_FORMAT_RGBA_4444:
321 src0_format = 0x6;
322 pixel_width = 2;
323 break;
324 case RGA2_FORMAT_BGR_565:
325 src0_format = 0x4;
326 pixel_width = 2;
327 msg->src_trans_mode &= 0x07;
328 src0_rb_swp = 0x1;
329 break;
330 case RGA2_FORMAT_BGRA_5551:
331 src0_format = 0x5;
332 pixel_width = 2;
333 src0_rb_swp = 0x1;
334 break;
335 case RGA2_FORMAT_BGRA_4444:
336 src0_format = 0x6;
337 pixel_width = 2;
338 src0_rb_swp = 0x1;
339 break;
340
341 /* ARGB */
342 /*
343 * In colorkey mode, xrgb/xbgr does not
344 * need to enable the alpha channel
345 */
346 case RGA2_FORMAT_ARGB_8888:
347 src0_format = 0x0;
348 pixel_width = 4;
349 src0_alpha_swp = 1;
350 break;
351 case RGA2_FORMAT_ABGR_8888:
352 src0_format = 0x0;
353 pixel_width = 4;
354 src0_alpha_swp = 1;
355 src0_rb_swp = 0x1;
356 break;
357 case RGA2_FORMAT_XRGB_8888:
358 src0_format = 0x1;
359 pixel_width = 4;
360 src0_alpha_swp = 1;
361 msg->src_trans_mode &= 0x07;
362 break;
363 case RGA2_FORMAT_XBGR_8888:
364 src0_format = 0x1;
365 pixel_width = 4;
366 src0_alpha_swp = 1;
367 src0_rb_swp = 0x1;
368 msg->src_trans_mode &= 0x07;
369 break;
370 case RGA2_FORMAT_ARGB_5551:
371 src0_format = 0x5;
372 pixel_width = 2;
373 src0_alpha_swp = 1;
374 break;
375 case RGA2_FORMAT_ABGR_5551:
376 src0_format = 0x5;
377 pixel_width = 2;
378 src0_alpha_swp = 1;
379 src0_rb_swp = 0x1;
380 break;
381 case RGA2_FORMAT_ARGB_4444:
382 src0_format = 0x6;
383 pixel_width = 2;
384 src0_alpha_swp = 1;
385 break;
386 case RGA2_FORMAT_ABGR_4444:
387 src0_format = 0x6;
388 pixel_width = 2;
389 src0_alpha_swp = 1;
390 src0_rb_swp = 0x1;
391 break;
392
393 case RGA2_FORMAT_YVYU_422:
394 src0_format = 0x7;
395 pixel_width = 2;
396 src0_cbcr_swp = 1;
397 src0_rb_swp = 0x1;
398 break; //rbswap=ycswap
399 case RGA2_FORMAT_VYUY_422:
400 src0_format = 0x7;
401 pixel_width = 2;
402 src0_cbcr_swp = 1;
403 src0_rb_swp = 0x0;
404 break;
405 case RGA2_FORMAT_YUYV_422:
406 src0_format = 0x7;
407 pixel_width = 2;
408 src0_cbcr_swp = 0;
409 src0_rb_swp = 0x1;
410 break;
411 case RGA2_FORMAT_UYVY_422:
412 src0_format = 0x7;
413 pixel_width = 2;
414 src0_cbcr_swp = 0;
415 src0_rb_swp = 0x0;
416 break;
417
418 case RGA2_FORMAT_YCbCr_422_SP:
419 src0_format = 0x8;
420 xdiv = 1;
421 ydiv = 1;
422 break;
423 case RGA2_FORMAT_YCbCr_422_P:
424 src0_format = 0x9;
425 xdiv = 2;
426 ydiv = 1;
427 break;
428 case RGA2_FORMAT_YCbCr_420_SP:
429 src0_format = 0xa;
430 xdiv = 1;
431 ydiv = 2;
432 break;
433 case RGA2_FORMAT_YCbCr_420_P:
434 src0_format = 0xb;
435 xdiv = 2;
436 ydiv = 2;
437 break;
438 case RGA2_FORMAT_YCrCb_422_SP:
439 src0_format = 0x8;
440 xdiv = 1;
441 ydiv = 1;
442 src0_cbcr_swp = 1;
443 break;
444 case RGA2_FORMAT_YCrCb_422_P:
445 src0_format = 0x9;
446 xdiv = 2;
447 ydiv = 1;
448 src0_cbcr_swp = 1;
449 break;
450 case RGA2_FORMAT_YCrCb_420_SP:
451 src0_format = 0xa;
452 xdiv = 1;
453 ydiv = 2;
454 src0_cbcr_swp = 1;
455 break;
456 case RGA2_FORMAT_YCrCb_420_P:
457 src0_format = 0xb;
458 xdiv = 2;
459 ydiv = 2;
460 src0_cbcr_swp = 1;
461 break;
462
463 case RGA2_FORMAT_YCbCr_420_SP_10B:
464 src0_format = 0xa;
465 xdiv = 1;
466 ydiv = 2;
467 yuv10 = 1;
468 break;
469 case RGA2_FORMAT_YCrCb_420_SP_10B:
470 src0_format = 0xa;
471 xdiv = 1;
472 ydiv = 2;
473 src0_cbcr_swp = 1;
474 yuv10 = 1;
475 break;
476 case RGA2_FORMAT_YCbCr_422_SP_10B:
477 src0_format = 0x8;
478 xdiv = 1;
479 ydiv = 1;
480 yuv10 = 1;
481 break;
482 case RGA2_FORMAT_YCrCb_422_SP_10B:
483 src0_format = 0x8;
484 xdiv = 1;
485 ydiv = 1;
486 src0_cbcr_swp = 1;
487 yuv10 = 1;
488 break;
489
490 case RGA2_FORMAT_YCbCr_400:
491 src0_format = 0x8;
492 src_fmt_yuv400_en = 1;
493 xdiv = 1;
494 ydiv = 1;
495 break;
496 };
497
498 reg =
499 ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) |
500 (s_RGA2_SRC_INFO_SW_SRC_FMT(src0_format)));
501 reg =
502 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP)) |
503 (s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(src0_rb_swp)));
504 reg =
505 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP)) |
506 (s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(src0_alpha_swp)));
507 reg =
508 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP)) |
509 (s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(src0_cbcr_swp)));
510 reg =
511 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) |
512 (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(msg->yuv2rgb_mode)));
513
514 reg =
515 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE)) |
516 (s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(msg->rotate_mode & 0x3)));
517 reg =
518 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE)) |
519 (s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE
520 ((msg->rotate_mode >> 4) & 0x3)));
521 reg =
522 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE)) |
523 (s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE((scale_w_flag))));
524 reg =
525 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE)) |
526 (s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE((scale_h_flag))));
527 reg =
528 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER)) |
529 (s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER((
530 msg->scale_bicu_mode))));
531 reg =
532 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE)) |
533 (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(msg->src_trans_mode)));
534 reg =
535 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E)) |
536 (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(msg->src_trans_mode >> 1)));
537 reg =
538 ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E)) |
539 (s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E
540 ((msg->alpha_rop_flag >> 4) & 0x1)));
541 reg =
542 ((reg & (~m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL)) |
543 (s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL((
544 msg->scale_bicu_mode >> 4))));
545 reg =
546 ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_E)) |
547 (s_RGA2_SRC_INFO_SW_SW_YUV10_E((yuv10))));
548
549 reg =
550 ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E)) |
551 (s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E((yuv10))));
552
553 RGA2_reg_get_param(base, msg);
554
555 stride = (((msg->src.vir_w * pixel_width) + 3) & ~3) >> 2;
556 uv_stride = ((msg->src.vir_w / xdiv + 3) & ~3);
557
558 if (src_fmt_yuv400_en == 1) {
559 /*
560 * When Y400 as the input format, because the current
561 * RGA does not support closing
562 * the access of the UV channel, the address of the UV
563 * channel access is equal to
564 * the address of the Y channel access to ensure that
565 * the UV channel can access,
566 * preventing the RGA hardware from reporting errors.
567 */
568 *bRGA_SRC_BASE0 =
569 (u32) (msg->src.yrgb_addr +
570 msg->src.y_offset * (stride << 2) +
571 msg->src.x_offset * pixel_width);
572 *bRGA_SRC_BASE1 = *bRGA_SRC_BASE0;
573 *bRGA_SRC_BASE2 = *bRGA_SRC_BASE0;
574 } else {
575 *bRGA_SRC_BASE0 =
576 (u32) (msg->src.yrgb_addr +
577 msg->src.y_offset * (stride << 2) +
578 msg->src.x_offset * pixel_width);
579 *bRGA_SRC_BASE1 =
580 (u32) (msg->src.uv_addr +
581 (msg->src.y_offset / ydiv) * uv_stride +
582 (msg->src.x_offset / xdiv));
583 *bRGA_SRC_BASE2 =
584 (u32) (msg->src.v_addr +
585 (msg->src.y_offset / ydiv) * uv_stride +
586 (msg->src.x_offset / xdiv));
587 }
588
589 //mask_stride = ((msg->src0_act.width + 31) & ~31) >> 5;
590 mask_stride = msg->rop_mask_stride;
591
592 *bRGA_SRC_VIR_INFO = stride | (mask_stride << 16);
593
594 *bRGA_SRC_ACT_INFO =
595 (msg->src.act_w - 1) | ((msg->src.act_h - 1) << 16);
596
597 *bRGA_MASK_ADDR = (u32) msg->rop_mask_addr;
598
599 *bRGA_SRC_INFO = reg;
600
601 *bRGA_SRC_TR_COLOR0 = msg->color_key_min;
602 *bRGA_SRC_TR_COLOR1 = msg->color_key_max;
603 }
604
RGA2_set_reg_dst_info(u8 * base,struct rga2_req * msg)605 static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
606 {
607 u32 *bRGA_DST_INFO;
608 u32 *bRGA_DST_BASE0, *bRGA_DST_BASE1, *bRGA_DST_BASE2,
609 *bRGA_SRC_BASE3;
610 u32 *bRGA_DST_VIR_INFO;
611 u32 *bRGA_DST_ACT_INFO;
612
613 u32 *RGA_DST_Y4MAP_LUT0; //Y4 LUT0
614 u32 *RGA_DST_Y4MAP_LUT1; //Y4 LUT1
615 u32 *RGA_DST_NN_QUANTIZE_SCALE;
616 u32 *RGA_DST_NN_QUANTIZE_OFFSET;
617
618 u32 line_width_real;
619
620 u8 ydither_en = 0;
621
622 u8 src1_format = 0;
623 u8 src1_rb_swp = 0;
624 u8 src1_alpha_swp = 0;
625
626 u8 dst_format = 0;
627 u8 dst_rb_swp = 0;
628 u8 dst_cbcr_swp = 0;
629 u8 dst_alpha_swp = 0;
630
631 u8 dst_fmt_yuv400_en = 0;
632 u8 dst_fmt_y4_en = 0;
633 u8 dst_nn_quantize_en = 0;
634
635 u32 reg = 0;
636 u8 spw, dpw;
637 u32 s_stride, d_stride;
638 u32 x_mirr, y_mirr, rot_90_flag;
639 u32 yrgb_addr, u_addr, v_addr, s_yrgb_addr;
640 u32 d_uv_stride, x_div, y_div;
641 u32 y_lt_addr, y_ld_addr, y_rt_addr, y_rd_addr;
642 u32 u_lt_addr, u_ld_addr, u_rt_addr, u_rd_addr;
643 u32 v_lt_addr, v_ld_addr, v_rt_addr, v_rd_addr;
644
645 dpw = 1;
646 x_div = y_div = 1;
647
648 dst_nn_quantize_en = (msg->alpha_rop_flag >> 8) & 0x1;
649
650 bRGA_DST_INFO = (u32 *) (base + RGA2_DST_INFO_OFFSET);
651 bRGA_DST_BASE0 = (u32 *) (base + RGA2_DST_BASE0_OFFSET);
652 bRGA_DST_BASE1 = (u32 *) (base + RGA2_DST_BASE1_OFFSET);
653 bRGA_DST_BASE2 = (u32 *) (base + RGA2_DST_BASE2_OFFSET);
654
655 bRGA_SRC_BASE3 = (u32 *) (base + RGA2_SRC_BASE3_OFFSET);
656
657 bRGA_DST_VIR_INFO = (u32 *) (base + RGA2_DST_VIR_INFO_OFFSET);
658 bRGA_DST_ACT_INFO = (u32 *) (base + RGA2_DST_ACT_INFO_OFFSET);
659
660 RGA_DST_Y4MAP_LUT0 = (u32 *) (base + RGA2_DST_Y4MAP_LUT0_OFFSET);
661 RGA_DST_Y4MAP_LUT1 = (u32 *) (base + RGA2_DST_Y4MAP_LUT1_OFFSET);
662 RGA_DST_NN_QUANTIZE_SCALE =
663 (u32 *) (base + RGA2_DST_QUANTIZE_SCALE_OFFSET);
664 RGA_DST_NN_QUANTIZE_OFFSET =
665 (u32 *) (base + RGA2_DST_QUANTIZE_OFFSET_OFFSET);
666
667 switch (msg->src1.format) {
668 case RGA2_FORMAT_RGBA_8888:
669 src1_format = 0x0;
670 spw = 4;
671 break;
672 case RGA2_FORMAT_BGRA_8888:
673 src1_format = 0x0;
674 src1_rb_swp = 0x1;
675 spw = 4;
676 break;
677 case RGA2_FORMAT_RGBX_8888:
678 src1_format = 0x1;
679 spw = 4;
680 break;
681 case RGA2_FORMAT_BGRX_8888:
682 src1_format = 0x1;
683 src1_rb_swp = 0x1;
684 spw = 4;
685 break;
686 case RGA2_FORMAT_RGB_888:
687 src1_format = 0x2;
688 spw = 3;
689 break;
690 case RGA2_FORMAT_BGR_888:
691 src1_format = 0x2;
692 src1_rb_swp = 1;
693 spw = 3;
694 break;
695 case RGA2_FORMAT_RGB_565:
696 src1_format = 0x4;
697 spw = 2;
698 break;
699 case RGA2_FORMAT_RGBA_5551:
700 src1_format = 0x5;
701 spw = 2;
702 break;
703 case RGA2_FORMAT_RGBA_4444:
704 src1_format = 0x6;
705 spw = 2;
706 break;
707 case RGA2_FORMAT_BGR_565:
708 src1_format = 0x4;
709 spw = 2;
710 src1_rb_swp = 0x1;
711 break;
712 case RGA2_FORMAT_BGRA_5551:
713 src1_format = 0x5;
714 spw = 2;
715 src1_rb_swp = 0x1;
716 break;
717 case RGA2_FORMAT_BGRA_4444:
718 src1_format = 0x6;
719 spw = 2;
720 src1_rb_swp = 0x1;
721 break;
722
723 /* ARGB */
724 case RGA2_FORMAT_ARGB_8888:
725 src1_format = 0x0;
726 spw = 4;
727 src1_alpha_swp = 1;
728 break;
729 case RGA2_FORMAT_ABGR_8888:
730 src1_format = 0x0;
731 spw = 4;
732 src1_alpha_swp = 1;
733 src1_rb_swp = 0x1;
734 break;
735 case RGA2_FORMAT_XRGB_8888:
736 src1_format = 0x1;
737 spw = 4;
738 src1_alpha_swp = 1;
739 break;
740 case RGA2_FORMAT_XBGR_8888:
741 src1_format = 0x1;
742 spw = 4;
743 src1_alpha_swp = 1;
744 src1_rb_swp = 0x1;
745 break;
746 case RGA2_FORMAT_ARGB_5551:
747 src1_format = 0x5;
748 spw = 2;
749 src1_alpha_swp = 1;
750 break;
751 case RGA2_FORMAT_ABGR_5551:
752 src1_format = 0x5;
753 spw = 2;
754 src1_alpha_swp = 1;
755 src1_rb_swp = 0x1;
756 break;
757 case RGA2_FORMAT_ARGB_4444:
758 src1_format = 0x6;
759 spw = 2;
760 src1_alpha_swp = 1;
761 break;
762 case RGA2_FORMAT_ABGR_4444:
763 src1_format = 0x6;
764 spw = 2;
765 src1_alpha_swp = 1;
766 src1_rb_swp = 0x1;
767 break;
768 default:
769 spw = 4;
770 break;
771 };
772
773 reg =
774 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_FMT)) |
775 (s_RGA2_DST_INFO_SW_SRC1_FMT(src1_format)));
776 reg =
777 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_RB_SWP)) |
778 (s_RGA2_DST_INFO_SW_SRC1_RB_SWP(src1_rb_swp)));
779 reg =
780 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP)) |
781 (s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(src1_alpha_swp)));
782
783 switch (msg->dst.format) {
784 case RGA2_FORMAT_RGBA_8888:
785 dst_format = 0x0;
786 dpw = 4;
787 break;
788 case RGA2_FORMAT_BGRA_8888:
789 dst_format = 0x0;
790 dst_rb_swp = 0x1;
791 dpw = 4;
792 break;
793 case RGA2_FORMAT_RGBX_8888:
794 dst_format = 0x1;
795 dpw = 4;
796 break;
797 case RGA2_FORMAT_BGRX_8888:
798 dst_format = 0x1;
799 dst_rb_swp = 0x1;
800 dpw = 4;
801 break;
802 case RGA2_FORMAT_RGB_888:
803 dst_format = 0x2;
804 dpw = 3;
805 break;
806 case RGA2_FORMAT_BGR_888:
807 dst_format = 0x2;
808 dst_rb_swp = 1;
809 dpw = 3;
810 break;
811 case RGA2_FORMAT_RGB_565:
812 dst_format = 0x4;
813 dpw = 2;
814 break;
815 case RGA2_FORMAT_RGBA_5551:
816 dst_format = 0x5;
817 dpw = 2;
818 break;
819 case RGA2_FORMAT_RGBA_4444:
820 dst_format = 0x6;
821 dpw = 2;
822 break;
823 case RGA2_FORMAT_BGR_565:
824 dst_format = 0x4;
825 dpw = 2;
826 dst_rb_swp = 0x1;
827 break;
828 case RGA2_FORMAT_BGRA_5551:
829 dst_format = 0x5;
830 dpw = 2;
831 dst_rb_swp = 0x1;
832 break;
833 case RGA2_FORMAT_BGRA_4444:
834 dst_format = 0x6;
835 dpw = 2;
836 dst_rb_swp = 0x1;
837 break;
838
839 /* ARGB */
840 case RGA2_FORMAT_ARGB_8888:
841 dst_format = 0x0;
842 dpw = 4;
843 dst_alpha_swp = 1;
844 break;
845 case RGA2_FORMAT_ABGR_8888:
846 dst_format = 0x0;
847 dpw = 4;
848 dst_alpha_swp = 1;
849 dst_rb_swp = 0x1;
850 break;
851 case RGA2_FORMAT_XRGB_8888:
852 dst_format = 0x1;
853 dpw = 4;
854 dst_alpha_swp = 1;
855 break;
856 case RGA2_FORMAT_XBGR_8888:
857 dst_format = 0x1;
858 dpw = 4;
859 dst_alpha_swp = 1;
860 dst_rb_swp = 0x1;
861 break;
862 case RGA2_FORMAT_ARGB_5551:
863 dst_format = 0x5;
864 dpw = 2;
865 dst_alpha_swp = 1;
866 break;
867 case RGA2_FORMAT_ABGR_5551:
868 dst_format = 0x5;
869 dpw = 2;
870 dst_alpha_swp = 1;
871 dst_rb_swp = 0x1;
872 break;
873 case RGA2_FORMAT_ARGB_4444:
874 dst_format = 0x6;
875 dpw = 2;
876 dst_alpha_swp = 1;
877 break;
878 case RGA2_FORMAT_ABGR_4444:
879 dst_format = 0x6;
880 dpw = 2;
881 dst_alpha_swp = 1;
882 dst_rb_swp = 0x1;
883 break;
884
885 case RGA2_FORMAT_YCbCr_422_SP:
886 dst_format = 0x8;
887 x_div = 1;
888 y_div = 1;
889 break;
890 case RGA2_FORMAT_YCbCr_422_P:
891 dst_format = 0x9;
892 x_div = 2;
893 y_div = 1;
894 break;
895 case RGA2_FORMAT_YCbCr_420_SP:
896 dst_format = 0xa;
897 x_div = 1;
898 y_div = 2;
899 break;
900 case RGA2_FORMAT_YCbCr_420_P:
901 dst_format = 0xb;
902 dst_cbcr_swp = 1;
903 x_div = 2;
904 y_div = 2;
905 break;
906 case RGA2_FORMAT_YCrCb_422_SP:
907 dst_format = 0x8;
908 dst_cbcr_swp = 1;
909 x_div = 1;
910 y_div = 1;
911 break;
912 case RGA2_FORMAT_YCrCb_422_P:
913 dst_format = 0x9;
914 dst_cbcr_swp = 1;
915 x_div = 2;
916 y_div = 1;
917 break;
918 case RGA2_FORMAT_YCrCb_420_SP:
919 dst_format = 0xa;
920 dst_cbcr_swp = 1;
921 x_div = 1;
922 y_div = 2;
923 break;
924 case RGA2_FORMAT_YCrCb_420_P:
925 dst_format = 0xb;
926 x_div = 2;
927 y_div = 2;
928 break;
929
930 case RGA2_FORMAT_YCbCr_400:
931 dst_format = 0x8;
932 dst_fmt_yuv400_en = 1;
933 x_div = 1;
934 y_div = 1;
935 break;
936 case RGA2_FORMAT_Y4:
937 dst_format = 0x8;
938 dst_fmt_y4_en = 1;
939 dst_fmt_yuv400_en = 1;
940 x_div = 1;
941 y_div = 1;
942 break;
943
944 case RGA2_FORMAT_YUYV_422:
945 dst_format = 0xe;
946 dpw = 2;
947 dst_cbcr_swp = 1;
948 break;
949 case RGA2_FORMAT_YVYU_422:
950 dst_format = 0xe;
951 dpw = 2;
952 break;
953 case RGA2_FORMAT_YUYV_420:
954 dst_format = 0xf;
955 dpw = 2;
956 dst_cbcr_swp = 1;
957 break;
958 case RGA2_FORMAT_YVYU_420:
959 dst_format = 0xf;
960 dpw = 2;
961 break;
962 case RGA2_FORMAT_UYVY_422:
963 dst_format = 0xc;
964 dpw = 2;
965 dst_cbcr_swp = 1;
966 break;
967 case RGA2_FORMAT_VYUY_422:
968 dst_format = 0xc;
969 dpw = 2;
970 break;
971 case RGA2_FORMAT_UYVY_420:
972 dst_format = 0xd;
973 dpw = 2;
974 dst_cbcr_swp = 1;
975 break;
976 case RGA2_FORMAT_VYUY_420:
977 dst_format = 0xd;
978 dpw = 2;
979 break;
980 };
981
982 reg =
983 ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT)) |
984 (s_RGA2_DST_INFO_SW_DST_FMT(dst_format)));
985 reg =
986 ((reg & (~m_RGA2_DST_INFO_SW_DST_RB_SWAP)) |
987 (s_RGA2_DST_INFO_SW_DST_RB_SWAP(dst_rb_swp)));
988 reg =
989 ((reg & (~m_RGA2_DST_INFO_SW_ALPHA_SWAP)) |
990 (s_RGA2_DST_INFO_SW_ALPHA_SWAP(dst_alpha_swp)));
991 reg =
992 ((reg & (~m_RGA2_DST_INFO_SW_DST_UV_SWAP)) |
993 (s_RGA2_DST_INFO_SW_DST_UV_SWAP(dst_cbcr_swp)));
994
995 reg =
996 ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN)) |
997 (s_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN(dst_fmt_yuv400_en)));
998 reg =
999 ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT_Y4_EN)) |
1000 (s_RGA2_DST_INFO_SW_DST_FMT_Y4_EN(dst_fmt_y4_en)));
1001 reg =
1002 ((reg & (~m_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN)) |
1003 (s_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN(dst_nn_quantize_en)));
1004 reg =
1005 ((reg & (~m_RGA2_DST_INFO_SW_DITHER_UP_E)) |
1006 (s_RGA2_DST_INFO_SW_DITHER_UP_E(msg->alpha_rop_flag >> 5)));
1007 reg =
1008 ((reg & (~m_RGA2_DST_INFO_SW_DITHER_DOWN_E)) |
1009 (s_RGA2_DST_INFO_SW_DITHER_DOWN_E(msg->alpha_rop_flag >> 6)));
1010 reg =
1011 ((reg & (~m_RGA2_DST_INFO_SW_DITHER_MODE)) |
1012 (s_RGA2_DST_INFO_SW_DITHER_MODE(msg->dither_mode)));
1013 reg =
1014 ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE)) |
1015 (s_RGA2_DST_INFO_SW_DST_CSC_MODE(msg->yuv2rgb_mode >> 2)));
1016 reg =
1017 ((reg & (~m_RGA2_DST_INFO_SW_CSC_CLIP_MODE)) |
1018 (s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(msg->yuv2rgb_mode >> 4)));
1019 /* full csc enable */
1020 reg =
1021 ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE_2)) |
1022 (s_RGA2_DST_INFO_SW_DST_CSC_MODE_2(msg->full_csc.flag)));
1023 /*
1024 * Some older chips do not support src1 csc mode,
1025 * they do not have these two registers.
1026 */
1027 reg =
1028 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_CSC_MODE)) |
1029 (s_RGA2_DST_INFO_SW_SRC1_CSC_MODE(msg->yuv2rgb_mode >> 5)));
1030 reg =
1031 ((reg & (~m_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE)) |
1032 (s_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE(
1033 msg->yuv2rgb_mode >> 7)));
1034
1035 ydither_en = (msg->dst.format == RGA2_FORMAT_Y4)
1036 && ((msg->alpha_rop_flag >> 6) & 0x1);
1037
1038 *bRGA_DST_INFO = reg;
1039
1040 s_stride = ((msg->src1.vir_w * spw + 3) & ~3) >> 2;
1041 d_stride = ((msg->dst.vir_w * dpw + 3) & ~3) >> 2;
1042
1043 if (dst_fmt_y4_en) {
1044 /* Y4 output will HALF */
1045 d_stride = ((d_stride + 1) & ~1) >> 1;
1046 }
1047
1048 d_uv_stride = (d_stride << 2) / x_div;
1049
1050 *bRGA_DST_VIR_INFO = d_stride | (s_stride << 16);
1051 if ((msg->dst.vir_w % 2 != 0) &&
1052 (msg->dst.act_w == msg->src.act_w)
1053 && (msg->dst.act_h == msg->src.act_h)
1054 && (msg->dst.format == RGA2_FORMAT_BGR_888
1055 || msg->dst.format == RGA2_FORMAT_RGB_888))
1056 *bRGA_DST_ACT_INFO =
1057 (msg->dst.act_w) | ((msg->dst.act_h - 1) << 16);
1058 else
1059 *bRGA_DST_ACT_INFO =
1060 (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);
1061 s_stride <<= 2;
1062 d_stride <<= 2;
1063
1064 if (((msg->rotate_mode & 0xf) == 0) ||
1065 ((msg->rotate_mode & 0xf) == 1)) {
1066 x_mirr = 0;
1067 y_mirr = 0;
1068 } else {
1069 x_mirr = 1;
1070 y_mirr = 1;
1071 }
1072
1073 rot_90_flag = msg->rotate_mode & 1;
1074 x_mirr = (x_mirr + ((msg->rotate_mode >> 4) & 1)) & 1;
1075 y_mirr = (y_mirr + ((msg->rotate_mode >> 5) & 1)) & 1;
1076
1077 if (ydither_en) {
1078 if (x_mirr && y_mirr) {
1079 pr_err("ydither mode do not support rotate x_mirr=%d,y_mirr=%d\n",
1080 x_mirr, y_mirr);
1081 }
1082
1083 if (msg->dst.act_w != msg->src.act_w)
1084 pr_err("ydither mode do not support x dir scale\n");
1085
1086 if (msg->dst.act_h != msg->src.act_h)
1087 pr_err("ydither mode do not support y dir scale\n");
1088 }
1089
1090 if (dst_fmt_y4_en) {
1091 *RGA_DST_Y4MAP_LUT0 = (msg->gr_color.gr_x_r & 0xffff) |
1092 (msg->gr_color.gr_x_g << 16);
1093 *RGA_DST_Y4MAP_LUT1 = (msg->gr_color.gr_y_r & 0xffff) |
1094 (msg->gr_color.gr_y_g << 16);
1095 }
1096
1097 if (dst_nn_quantize_en) {
1098 *RGA_DST_NN_QUANTIZE_SCALE = (msg->gr_color.gr_x_r & 0xffff) |
1099 (msg->gr_color.gr_x_g << 10) |
1100 (msg->gr_color.gr_x_b << 20);
1101 *RGA_DST_NN_QUANTIZE_OFFSET = (msg->gr_color.gr_y_r & 0xffff) |
1102 (msg->gr_color.gr_y_g << 10) |
1103 (msg->gr_color.gr_y_b << 20);
1104 }
1105
1106 s_yrgb_addr =
1107 (u32) msg->src1.yrgb_addr + (msg->src1.y_offset * s_stride) +
1108 (msg->src1.x_offset * spw);
1109
1110 *bRGA_SRC_BASE3 = s_yrgb_addr;
1111
1112 if (dst_fmt_y4_en) {
1113 yrgb_addr = (u32) msg->dst.yrgb_addr +
1114 (msg->dst.y_offset * d_stride) +
1115 ((msg->dst.x_offset * dpw) >> 1);
1116 } else {
1117 yrgb_addr = (u32) msg->dst.yrgb_addr +
1118 (msg->dst.y_offset * d_stride) +
1119 (msg->dst.x_offset * dpw);
1120 }
1121 u_addr = (u32) msg->dst.uv_addr +
1122 (msg->dst.y_offset / y_div) * d_uv_stride +
1123 msg->dst.x_offset / x_div;
1124 v_addr = (u32) msg->dst.v_addr +
1125 (msg->dst.y_offset / y_div) * d_uv_stride +
1126 msg->dst.x_offset / x_div;
1127
1128 y_lt_addr = yrgb_addr;
1129 u_lt_addr = u_addr;
1130 v_lt_addr = v_addr;
1131
1132 /* Warning */
1133 line_width_real =
1134 dst_fmt_y4_en ? ((msg->dst.act_w) >> 1) : msg->dst.act_w;
1135
1136 if (msg->dst.format < 0x18 ||
1137 (msg->dst.format >= RGA2_FORMAT_ARGB_8888 &&
1138 msg->dst.format <= RGA2_FORMAT_ABGR_4444)) {
1139 /* 270 degree & Mirror V */
1140 y_ld_addr = yrgb_addr + (msg->dst.act_h - 1) * (d_stride);
1141 /* 90 degree & Mirror H */
1142 y_rt_addr = yrgb_addr + (line_width_real - 1) * dpw;
1143 /* 180 degree */
1144 y_rd_addr = y_ld_addr + (line_width_real - 1) * dpw;
1145 } else {
1146 if (msg->dst.format == RGA2_FORMAT_YUYV_422 ||
1147 msg->dst.format == RGA2_FORMAT_YVYU_422 ||
1148 msg->dst.format == RGA2_FORMAT_UYVY_422 ||
1149 msg->dst.format == RGA2_FORMAT_VYUY_422) {
1150 y_ld_addr =
1151 yrgb_addr + (msg->dst.act_h - 1) * (d_stride);
1152 y_rt_addr = yrgb_addr + (msg->dst.act_w * 2 - 1);
1153 y_rd_addr = y_ld_addr + (msg->dst.act_w * 2 - 1);
1154 } else {
1155 y_ld_addr = (u32) msg->dst.yrgb_addr +
1156 ((msg->dst.y_offset +
1157 (msg->dst.act_h - 1)) * d_stride) +
1158 msg->dst.x_offset;
1159 y_rt_addr = yrgb_addr + (msg->dst.act_w * 2 - 1);
1160 y_rd_addr = y_ld_addr + (msg->dst.act_w - 1);
1161 }
1162 }
1163
1164 u_ld_addr = u_addr + ((msg->dst.act_h / y_div) - 1) * (d_uv_stride);
1165 v_ld_addr = v_addr + ((msg->dst.act_h / y_div) - 1) * (d_uv_stride);
1166
1167 u_rt_addr = u_addr + (msg->dst.act_w / x_div) - 1;
1168 v_rt_addr = v_addr + (msg->dst.act_w / x_div) - 1;
1169
1170 u_rd_addr = u_ld_addr + (msg->dst.act_w / x_div) - 1;
1171 v_rd_addr = v_ld_addr + (msg->dst.act_w / x_div) - 1;
1172
1173 if (rot_90_flag == 0) {
1174 if (y_mirr == 1) {
1175 if (x_mirr == 1) {
1176 yrgb_addr = y_rd_addr;
1177 u_addr = u_rd_addr;
1178 v_addr = v_rd_addr;
1179 } else {
1180 yrgb_addr = y_ld_addr;
1181 u_addr = u_ld_addr;
1182 v_addr = v_ld_addr;
1183 }
1184 } else {
1185 if (x_mirr == 1) {
1186 yrgb_addr = y_rt_addr;
1187 u_addr = u_rt_addr;
1188 v_addr = v_rt_addr;
1189 } else {
1190 yrgb_addr = y_lt_addr;
1191 u_addr = u_lt_addr;
1192 v_addr = v_lt_addr;
1193 }
1194 }
1195 } else {
1196 if (y_mirr == 1) {
1197 if (x_mirr == 1) {
1198 yrgb_addr = y_ld_addr;
1199 u_addr = u_ld_addr;
1200 v_addr = v_ld_addr;
1201 } else {
1202 yrgb_addr = y_rd_addr;
1203 u_addr = u_rd_addr;
1204 v_addr = v_rd_addr;
1205 }
1206 } else {
1207 if (x_mirr == 1) {
1208 yrgb_addr = y_lt_addr;
1209 u_addr = u_lt_addr;
1210 v_addr = v_lt_addr;
1211 } else {
1212 yrgb_addr = y_rt_addr;
1213 u_addr = u_rt_addr;
1214 v_addr = v_rt_addr;
1215 }
1216 }
1217 }
1218
1219 *bRGA_DST_BASE0 = (u32) yrgb_addr;
1220
1221 if ((msg->dst.format == RGA2_FORMAT_YCbCr_420_P)
1222 || (msg->dst.format == RGA2_FORMAT_YCrCb_420_P)) {
1223 if (dst_cbcr_swp == 0) {
1224 *bRGA_DST_BASE1 = (u32) v_addr;
1225 *bRGA_DST_BASE2 = (u32) u_addr;
1226 } else {
1227 *bRGA_DST_BASE1 = (u32) u_addr;
1228 *bRGA_DST_BASE2 = (u32) v_addr;
1229 }
1230 } else {
1231 *bRGA_DST_BASE1 = (u32) u_addr;
1232 *bRGA_DST_BASE2 = (u32) v_addr;
1233 }
1234 }
1235
RGA2_set_reg_alpha_info(u8 * base,struct rga2_req * msg)1236 static void RGA2_set_reg_alpha_info(u8 *base, struct rga2_req *msg)
1237 {
1238 u32 *bRGA_ALPHA_CTRL0;
1239 u32 *bRGA_ALPHA_CTRL1;
1240 u32 *bRGA_FADING_CTRL;
1241 u32 reg0 = 0;
1242 u32 reg1 = 0;
1243
1244 bRGA_ALPHA_CTRL0 = (u32 *) (base + RGA2_ALPHA_CTRL0_OFFSET);
1245 bRGA_ALPHA_CTRL1 = (u32 *) (base + RGA2_ALPHA_CTRL1_OFFSET);
1246 bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1247
1248 reg0 =
1249 ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) |
1250 (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(msg->alpha_rop_flag)));
1251 reg0 =
1252 ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) |
1253 (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL
1254 (msg->alpha_rop_flag >> 1)));
1255 reg0 =
1256 ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) |
1257 (s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(msg->rop_mode)));
1258 reg0 =
1259 ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) |
1260 (s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA
1261 (msg->src_a_global_val)));
1262 reg0 =
1263 ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) |
1264 (s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA
1265 (msg->dst_a_global_val)));
1266
1267 reg1 =
1268 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0)) |
1269 (s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0
1270 (msg->alpha_mode_0 >> 15)));
1271 reg1 =
1272 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0)) |
1273 (s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0
1274 (msg->alpha_mode_0 >> 7)));
1275 reg1 =
1276 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0)) |
1277 (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0
1278 (msg->alpha_mode_0 >> 12)));
1279 reg1 =
1280 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0)) |
1281 (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0
1282 (msg->alpha_mode_0 >> 4)));
1283 reg1 =
1284 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0)) |
1285 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0
1286 (msg->alpha_mode_0 >> 11)));
1287 reg1 =
1288 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0)) |
1289 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0
1290 (msg->alpha_mode_0 >> 3)));
1291 reg1 =
1292 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0)) |
1293 (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0
1294 (msg->alpha_mode_0 >> 9)));
1295 reg1 =
1296 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0)) |
1297 (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0
1298 (msg->alpha_mode_0 >> 1)));
1299 reg1 =
1300 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0)) |
1301 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0
1302 (msg->alpha_mode_0 >> 8)));
1303 reg1 =
1304 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0)) |
1305 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0
1306 (msg->alpha_mode_0 >> 0)));
1307
1308 reg1 =
1309 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1)) |
1310 (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1
1311 (msg->alpha_mode_1 >> 12)));
1312 reg1 =
1313 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1)) |
1314 (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1
1315 (msg->alpha_mode_1 >> 4)));
1316 reg1 =
1317 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1)) |
1318 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1
1319 (msg->alpha_mode_1 >> 11)));
1320 reg1 =
1321 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1)) |
1322 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1
1323 (msg->alpha_mode_1 >> 3)));
1324 reg1 =
1325 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1)) |
1326 (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(msg->alpha_mode_1 >> 9)));
1327 reg1 =
1328 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1)) |
1329 (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(msg->alpha_mode_1 >> 1)));
1330 reg1 =
1331 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1)) |
1332 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(msg->alpha_mode_1 >> 8)));
1333 reg1 =
1334 ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1)) |
1335 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(msg->alpha_mode_1 >> 0)));
1336
1337 *bRGA_ALPHA_CTRL0 = reg0;
1338 *bRGA_ALPHA_CTRL1 = reg1;
1339
1340 if ((msg->alpha_rop_flag >> 2) & 1) {
1341 *bRGA_FADING_CTRL = (1 << 24) | (msg->fading_b_value << 16) |
1342 (msg->fading_g_value << 8) | (msg->fading_r_value);
1343 }
1344 }
1345
RGA2_set_reg_rop_info(u8 * base,struct rga2_req * msg)1346 static void RGA2_set_reg_rop_info(u8 *base, struct rga2_req *msg)
1347 {
1348 u32 *bRGA_ALPHA_CTRL0;
1349 u32 *bRGA_ROP_CTRL0;
1350 u32 *bRGA_ROP_CTRL1;
1351 u32 *bRGA_MASK_ADDR;
1352 u32 *bRGA_FG_COLOR;
1353 u32 *bRGA_PAT_CON;
1354
1355 u32 rop_code0 = 0;
1356 u32 rop_code1 = 0;
1357
1358 bRGA_ALPHA_CTRL0 = (u32 *) (base + RGA2_ALPHA_CTRL0_OFFSET);
1359 bRGA_ROP_CTRL0 = (u32 *) (base + RGA2_ROP_CTRL0_OFFSET);
1360 bRGA_ROP_CTRL1 = (u32 *) (base + RGA2_ROP_CTRL1_OFFSET);
1361 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
1362 bRGA_FG_COLOR = (u32 *) (base + RGA2_SRC_FG_COLOR_OFFSET);
1363 bRGA_PAT_CON = (u32 *) (base + RGA2_PAT_CON_OFFSET);
1364
1365 if (msg->rop_mode == 0) {
1366 rop_code0 = rga2_rop_code[(msg->rop_code & 0xff)];
1367 } else if (msg->rop_mode == 1) {
1368 rop_code0 = rga2_rop_code[(msg->rop_code & 0xff)];
1369 } else if (msg->rop_mode == 2) {
1370 rop_code0 = rga2_rop_code[(msg->rop_code & 0xff)];
1371 rop_code1 = rga2_rop_code[(msg->rop_code & 0xff00) >> 8];
1372 }
1373
1374 *bRGA_ROP_CTRL0 = rop_code0;
1375 *bRGA_ROP_CTRL1 = rop_code1;
1376 *bRGA_FG_COLOR = msg->fg_color;
1377 *bRGA_MASK_ADDR = (u32) msg->rop_mask_addr;
1378 *bRGA_PAT_CON = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8)
1379 | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
1380 *bRGA_ALPHA_CTRL0 =
1381 *bRGA_ALPHA_CTRL0 | (((msg->endian_mode >> 1) & 1) << 20);
1382
1383 }
1384
RGA2_set_reg_full_csc(u8 * base,struct rga2_req * msg)1385 static void RGA2_set_reg_full_csc(u8 *base, struct rga2_req *msg)
1386 {
1387 u32 *bRGA2_DST_CSC_00;
1388 u32 *bRGA2_DST_CSC_01;
1389 u32 *bRGA2_DST_CSC_02;
1390 u32 *bRGA2_DST_CSC_OFF0;
1391
1392 u32 *bRGA2_DST_CSC_10;
1393 u32 *bRGA2_DST_CSC_11;
1394 u32 *bRGA2_DST_CSC_12;
1395 u32 *bRGA2_DST_CSC_OFF1;
1396
1397 u32 *bRGA2_DST_CSC_20;
1398 u32 *bRGA2_DST_CSC_21;
1399 u32 *bRGA2_DST_CSC_22;
1400 u32 *bRGA2_DST_CSC_OFF2;
1401
1402 bRGA2_DST_CSC_00 = (u32 *) (base + RGA2_DST_CSC_00_OFFSET);
1403 bRGA2_DST_CSC_01 = (u32 *) (base + RGA2_DST_CSC_01_OFFSET);
1404 bRGA2_DST_CSC_02 = (u32 *) (base + RGA2_DST_CSC_02_OFFSET);
1405 bRGA2_DST_CSC_OFF0 = (u32 *) (base + RGA2_DST_CSC_OFF0_OFFSET);
1406
1407 bRGA2_DST_CSC_10 = (u32 *) (base + RGA2_DST_CSC_10_OFFSET);
1408 bRGA2_DST_CSC_11 = (u32 *) (base + RGA2_DST_CSC_11_OFFSET);
1409 bRGA2_DST_CSC_12 = (u32 *) (base + RGA2_DST_CSC_12_OFFSET);
1410 bRGA2_DST_CSC_OFF1 = (u32 *) (base + RGA2_DST_CSC_OFF1_OFFSET);
1411
1412 bRGA2_DST_CSC_20 = (u32 *) (base + RGA2_DST_CSC_20_OFFSET);
1413 bRGA2_DST_CSC_21 = (u32 *) (base + RGA2_DST_CSC_21_OFFSET);
1414 bRGA2_DST_CSC_22 = (u32 *) (base + RGA2_DST_CSC_22_OFFSET);
1415 bRGA2_DST_CSC_OFF2 = (u32 *) (base + RGA2_DST_CSC_OFF2_OFFSET);
1416
1417 /* full csc coefficient */
1418 /* Y coefficient */
1419 *bRGA2_DST_CSC_00 = msg->full_csc.coe_y.r_v;
1420 *bRGA2_DST_CSC_01 = msg->full_csc.coe_y.g_y;
1421 *bRGA2_DST_CSC_02 = msg->full_csc.coe_y.b_u;
1422 *bRGA2_DST_CSC_OFF0 = msg->full_csc.coe_y.off;
1423 /* U coefficient */
1424 *bRGA2_DST_CSC_10 = msg->full_csc.coe_u.r_v;
1425 *bRGA2_DST_CSC_11 = msg->full_csc.coe_u.g_y;
1426 *bRGA2_DST_CSC_12 = msg->full_csc.coe_u.b_u;
1427 *bRGA2_DST_CSC_OFF1 = msg->full_csc.coe_u.off;
1428 /* V coefficient */
1429 *bRGA2_DST_CSC_20 = msg->full_csc.coe_v.r_v;
1430 *bRGA2_DST_CSC_21 = msg->full_csc.coe_v.g_y;
1431 *bRGA2_DST_CSC_22 = msg->full_csc.coe_v.b_u;
1432 *bRGA2_DST_CSC_OFF2 = msg->full_csc.coe_v.off;
1433 }
1434
RGA2_set_reg_color_palette(u8 * base,struct rga2_req * msg)1435 static void RGA2_set_reg_color_palette(u8 *base, struct rga2_req *msg)
1436 {
1437 u32 *bRGA_SRC_BASE0, *bRGA_SRC_INFO, *bRGA_SRC_VIR_INFO,
1438 *bRGA_SRC_ACT_INFO, *bRGA_SRC_FG_COLOR, *bRGA_SRC_BG_COLOR;
1439 u32 *p;
1440 short x_off, y_off;
1441 u16 src_stride;
1442 u8 shift;
1443 u32 sw;
1444 u32 byte_num;
1445 u32 reg;
1446
1447 bRGA_SRC_BASE0 = (u32 *) (base + RGA2_SRC_BASE0_OFFSET);
1448 bRGA_SRC_INFO = (u32 *) (base + RGA2_SRC_INFO_OFFSET);
1449 bRGA_SRC_VIR_INFO = (u32 *) (base + RGA2_SRC_VIR_INFO_OFFSET);
1450 bRGA_SRC_ACT_INFO = (u32 *) (base + RGA2_SRC_ACT_INFO_OFFSET);
1451 bRGA_SRC_FG_COLOR = (u32 *) (base + RGA2_SRC_FG_COLOR_OFFSET);
1452 bRGA_SRC_BG_COLOR = (u32 *) (base + RGA2_SRC_BG_COLOR_OFFSET);
1453
1454 reg = 0;
1455
1456 shift = 3 - msg->palette_mode;
1457
1458 x_off = msg->src.x_offset;
1459 y_off = msg->src.y_offset;
1460
1461 sw = msg->src.vir_w;
1462 byte_num = sw >> shift;
1463
1464 src_stride = (byte_num + 3) & (~3);
1465
1466 p = (u32 *) ((unsigned long)msg->src.yrgb_addr);
1467
1468 p = p + (x_off >> shift) + y_off * src_stride;
1469
1470 *bRGA_SRC_BASE0 = (unsigned long)p;
1471
1472 reg =
1473 ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) |
1474 (s_RGA2_SRC_INFO_SW_SRC_FMT((msg->palette_mode | 0xc))));
1475 reg =
1476 ((reg & (~m_RGA2_SRC_INFO_SW_SW_CP_ENDAIN)) |
1477 (s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(msg->endian_mode & 1)));
1478 *bRGA_SRC_VIR_INFO = src_stride >> 2;
1479 *bRGA_SRC_ACT_INFO =
1480 (msg->src.act_w - 1) | ((msg->src.act_h - 1) << 16);
1481 *bRGA_SRC_INFO = reg;
1482
1483 *bRGA_SRC_FG_COLOR = msg->fg_color;
1484 *bRGA_SRC_BG_COLOR = msg->bg_color;
1485
1486 }
1487
RGA2_set_reg_color_fill(u8 * base,struct rga2_req * msg)1488 static void RGA2_set_reg_color_fill(u8 *base, struct rga2_req *msg)
1489 {
1490 u32 *bRGA_CF_GR_A;
1491 u32 *bRGA_CF_GR_B;
1492 u32 *bRGA_CF_GR_G;
1493 u32 *bRGA_CF_GR_R;
1494 u32 *bRGA_SRC_FG_COLOR;
1495 u32 *bRGA_MASK_ADDR;
1496 u32 *bRGA_PAT_CON;
1497
1498 u32 mask_stride;
1499 u32 *bRGA_SRC_VIR_INFO;
1500
1501 bRGA_SRC_FG_COLOR = (u32 *) (base + RGA2_SRC_FG_COLOR_OFFSET);
1502
1503 bRGA_CF_GR_A = (u32 *) (base + RGA2_CF_GR_A_OFFSET);
1504 bRGA_CF_GR_B = (u32 *) (base + RGA2_CF_GR_B_OFFSET);
1505 bRGA_CF_GR_G = (u32 *) (base + RGA2_CF_GR_G_OFFSET);
1506 bRGA_CF_GR_R = (u32 *) (base + RGA2_CF_GR_R_OFFSET);
1507
1508 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
1509 bRGA_PAT_CON = (u32 *) (base + RGA2_PAT_CON_OFFSET);
1510
1511 bRGA_SRC_VIR_INFO = (u32 *) (base + RGA2_SRC_VIR_INFO_OFFSET);
1512
1513 mask_stride = msg->rop_mask_stride;
1514
1515 if (msg->color_fill_mode == 0) {
1516 /* solid color */
1517 *bRGA_CF_GR_A = (msg->gr_color.gr_x_a & 0xffff) |
1518 (msg->gr_color.gr_y_a << 16);
1519 *bRGA_CF_GR_B = (msg->gr_color.gr_x_b & 0xffff) |
1520 (msg->gr_color.gr_y_b << 16);
1521 *bRGA_CF_GR_G = (msg->gr_color.gr_x_g & 0xffff) |
1522 (msg->gr_color.gr_y_g << 16);
1523 *bRGA_CF_GR_R = (msg->gr_color.gr_x_r & 0xffff) |
1524 (msg->gr_color.gr_y_r << 16);
1525
1526 *bRGA_SRC_FG_COLOR = msg->fg_color;
1527 } else {
1528 /* pattern color */
1529 *bRGA_MASK_ADDR = (u32) msg->pat.yrgb_addr;
1530 *bRGA_PAT_CON =
1531 (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8)
1532 | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
1533 }
1534 *bRGA_SRC_VIR_INFO = mask_stride << 16;
1535 }
1536
RGA2_set_reg_update_palette_table(u8 * base,struct rga2_req * msg)1537 static void RGA2_set_reg_update_palette_table(u8 *base,
1538 struct rga2_req *msg)
1539 {
1540 u32 *bRGA_MASK_BASE;
1541 u32 *bRGA_FADING_CTRL;
1542
1543 bRGA_MASK_BASE = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
1544 bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1545
1546 *bRGA_FADING_CTRL = msg->fading_g_value << 8;
1547 *bRGA_MASK_BASE = (u32) msg->pat.yrgb_addr;
1548 }
1549
RGA2_set_reg_update_patten_buff(u8 * base,struct rga2_req * msg)1550 static void RGA2_set_reg_update_patten_buff(u8 *base, struct rga2_req *msg)
1551 {
1552 u32 *bRGA_PAT_MST;
1553 u32 *bRGA_PAT_CON;
1554 u32 *bRGA_PAT_START_POINT;
1555 u32 *bRGA_FADING_CTRL;
1556 u32 reg = 0;
1557 struct rga_img_info_t *pat;
1558
1559 u32 num, offset;
1560
1561 pat = &msg->pat;
1562
1563 num = (pat->act_w * pat->act_h) - 1;
1564
1565 offset = pat->act_w * pat->y_offset + pat->x_offset;
1566
1567 bRGA_PAT_START_POINT = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1568 bRGA_PAT_MST = (u32 *) (base + RGA2_MASK_BASE_OFFSET);
1569 bRGA_PAT_CON = (u32 *) (base + RGA2_PAT_CON_OFFSET);
1570 bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1571
1572 *bRGA_PAT_MST = (u32) msg->pat.yrgb_addr;
1573 *bRGA_PAT_START_POINT = (pat->act_w * pat->y_offset) + pat->x_offset;
1574
1575 reg = (pat->act_w - 1) | ((pat->act_h - 1) << 8) |
1576 (pat->x_offset << 16) | (pat->y_offset << 24);
1577 *bRGA_PAT_CON = reg;
1578
1579 *bRGA_FADING_CTRL = (num << 8) | offset;
1580 }
1581
RGA2_set_pat_info(u8 * base,struct rga2_req * msg)1582 static void RGA2_set_pat_info(u8 *base, struct rga2_req *msg)
1583 {
1584 u32 *bRGA_PAT_CON;
1585 u32 *bRGA_FADING_CTRL;
1586 u32 reg = 0;
1587 struct rga_img_info_t *pat;
1588
1589 u32 num, offset;
1590
1591 pat = &msg->pat;
1592
1593 num = ((pat->act_w * pat->act_h) - 1) & 0xff;
1594
1595 offset = (pat->act_w * pat->y_offset) + pat->x_offset;
1596
1597 bRGA_PAT_CON = (u32 *) (base + RGA2_PAT_CON_OFFSET);
1598 bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
1599
1600 reg = (pat->act_w - 1) | ((pat->act_h - 1) << 8) |
1601 (pat->x_offset << 16) | (pat->y_offset << 24);
1602 *bRGA_PAT_CON = reg;
1603 *bRGA_FADING_CTRL = (num << 8) | offset;
1604 }
1605
RGA2_set_mmu_reg_info(u8 * base,struct rga2_req * msg)1606 static void RGA2_set_mmu_reg_info(u8 *base, struct rga2_req *msg)
1607 {
1608 u32 *bRGA_MMU_CTRL1;
1609 u32 *bRGA_MMU_SRC_BASE;
1610 u32 *bRGA_MMU_SRC1_BASE;
1611 u32 *bRGA_MMU_DST_BASE;
1612 u32 *bRGA_MMU_ELS_BASE;
1613
1614 u32 reg;
1615
1616 bRGA_MMU_CTRL1 = (u32 *) (base + RGA2_MMU_CTRL1_OFFSET);
1617 bRGA_MMU_SRC_BASE = (u32 *) (base + RGA2_MMU_SRC_BASE_OFFSET);
1618 bRGA_MMU_SRC1_BASE = (u32 *) (base + RGA2_MMU_SRC1_BASE_OFFSET);
1619 bRGA_MMU_DST_BASE = (u32 *) (base + RGA2_MMU_DST_BASE_OFFSET);
1620 bRGA_MMU_ELS_BASE = (u32 *) (base + RGA2_MMU_ELS_BASE_OFFSET);
1621
1622 reg = (msg->mmu_info.src0_mmu_flag & 0xf) |
1623 ((msg->mmu_info.src1_mmu_flag & 0xf) << 4) |
1624 ((msg->mmu_info.dst_mmu_flag & 0xf) << 8) |
1625 ((msg->mmu_info.els_mmu_flag & 0x3) << 12);
1626
1627 *bRGA_MMU_CTRL1 = reg;
1628 *bRGA_MMU_SRC_BASE = (u32) (msg->mmu_info.src0_base_addr) >> 4;
1629 *bRGA_MMU_SRC1_BASE = (u32) (msg->mmu_info.src1_base_addr) >> 4;
1630 *bRGA_MMU_DST_BASE = (u32) (msg->mmu_info.dst_base_addr) >> 4;
1631 *bRGA_MMU_ELS_BASE = (u32) (msg->mmu_info.els_base_addr) >> 4;
1632 }
1633
rga2_gen_reg_info(u8 * base,u8 * csc_base,struct rga2_req * msg)1634 int rga2_gen_reg_info(u8 *base, u8 *csc_base, struct rga2_req *msg)
1635 {
1636 u8 dst_nn_quantize_en = 0;
1637
1638 RGA2_set_mode_ctrl(base, msg);
1639
1640 RGA2_set_pat_info(base, msg);
1641
1642 switch (msg->render_mode) {
1643 case BITBLT_MODE:
1644 RGA2_set_reg_src_info(base, msg);
1645 RGA2_set_reg_dst_info(base, msg);
1646 dst_nn_quantize_en = (msg->alpha_rop_flag >> 8) & 0x1;
1647 if (dst_nn_quantize_en != 1) {
1648 if ((msg->dst.format !=
1649 RGA2_FORMAT_Y4)) {
1650 RGA2_set_reg_alpha_info(base, msg);
1651 RGA2_set_reg_rop_info(base, msg);
1652 }
1653
1654 if (msg->full_csc.flag)
1655 RGA2_set_reg_full_csc(csc_base, msg);
1656 }
1657 break;
1658 case COLOR_FILL_MODE:
1659 RGA2_set_reg_color_fill(base, msg);
1660 RGA2_set_reg_dst_info(base, msg);
1661 RGA2_set_reg_alpha_info(base, msg);
1662 break;
1663 case COLOR_PALETTE_MODE:
1664 RGA2_set_reg_color_palette(base, msg);
1665 RGA2_set_reg_dst_info(base, msg);
1666 break;
1667 case UPDATE_PALETTE_TABLE_MODE:
1668 RGA2_set_reg_update_palette_table(base, msg);
1669 break;
1670 case UPDATE_PATTEN_BUF_MODE:
1671 RGA2_set_reg_update_patten_buff(base, msg);
1672 break;
1673 default:
1674 pr_err("ERROR msg render mode %d\n", msg->render_mode);
1675 break;
1676 }
1677
1678 RGA2_set_mmu_reg_info(base, msg);
1679
1680 return 0;
1681 }
1682
rga_cmd_to_rga2_cmd(struct rga_req * req_rga,struct rga2_req * req)1683 void rga_cmd_to_rga2_cmd(struct rga_req *req_rga, struct rga2_req *req)
1684 {
1685 u16 alpha_mode_0, alpha_mode_1;
1686
1687 if (req_rga->render_mode == 6)
1688 req->render_mode = UPDATE_PALETTE_TABLE_MODE;
1689 else if (req_rga->render_mode == 7)
1690 req->render_mode = UPDATE_PATTEN_BUF_MODE;
1691 else if (req_rga->render_mode == 5)
1692 req->render_mode = BITBLT_MODE;
1693 else
1694 req->render_mode = req_rga->render_mode;
1695
1696 memcpy(&req->src, &req_rga->src, sizeof(req_rga->src));
1697 memcpy(&req->dst, &req_rga->dst, sizeof(req_rga->dst));
1698 /* The application will only import pat or src1. */
1699 if (req->render_mode == UPDATE_PALETTE_TABLE_MODE)
1700 memcpy(&req->pat, &req_rga->pat, sizeof(req_rga->pat));
1701 else
1702 memcpy(&req->src1, &req_rga->pat, sizeof(req_rga->pat));
1703
1704 user_format_convert(&req->src.format, req_rga->src.format);
1705 user_format_convert(&req->dst.format, req_rga->dst.format);
1706 user_format_convert(&req->src1.format, req_rga->pat.format);
1707
1708 switch (req_rga->rotate_mode & 0x0F) {
1709 case 1:
1710 if (req_rga->sina == 0 && req_rga->cosa == 65536) {
1711 /* rotate 0 */
1712 req->rotate_mode = 0;
1713 } else if (req_rga->sina == 65536 && req_rga->cosa == 0) {
1714 /* rotate 90 */
1715 req->rotate_mode = 1;
1716 req->dst.x_offset = req_rga->dst.x_offset;
1717 req->dst.act_w = req_rga->dst.act_h;
1718 req->dst.act_h = req_rga->dst.act_w;
1719 } else if (req_rga->sina == 0 && req_rga->cosa == -65536) {
1720 /* rotate 180 */
1721 req->rotate_mode = 2;
1722 req->dst.x_offset = req_rga->dst.x_offset;
1723 req->dst.y_offset = req_rga->dst.y_offset;
1724 } else if (req_rga->sina == -65536 && req_rga->cosa == 0) {
1725 /* totate 270 */
1726 req->rotate_mode = 3;
1727 req->dst.y_offset = req_rga->dst.y_offset;
1728 req->dst.act_w = req_rga->dst.act_h;
1729 req->dst.act_h = req_rga->dst.act_w;
1730 }
1731 break;
1732 case 2:
1733 //x_mirror
1734 req->rotate_mode |= (1 << 4);
1735 break;
1736 case 3:
1737 //y_mirror
1738 req->rotate_mode |= (2 << 4);
1739 break;
1740 case 4:
1741 //x_mirror+y_mirror
1742 req->rotate_mode |= (3 << 4);
1743 break;
1744 default:
1745 req->rotate_mode = 0;
1746 break;
1747 }
1748
1749 switch ((req_rga->rotate_mode & 0xF0) >> 4) {
1750 case 2:
1751 //x_mirror
1752 req->rotate_mode |= (1 << 4);
1753 break;
1754 case 3:
1755 //y_mirror
1756 req->rotate_mode |= (2 << 4);
1757 break;
1758 case 4:
1759 //x_mirror+y_mirror
1760 req->rotate_mode |= (3 << 4);
1761 break;
1762 }
1763
1764 if ((req->dst.act_w > 2048) && (req->src.act_h < req->dst.act_h))
1765 req->scale_bicu_mode |= (1 << 4);
1766
1767 req->LUT_addr = req_rga->LUT_addr;
1768 req->rop_mask_addr = req_rga->rop_mask_addr;
1769
1770 req->bitblt_mode = req_rga->bsfilter_flag;
1771
1772 req->src_a_global_val = req_rga->alpha_global_value;
1773 req->dst_a_global_val = req_rga->alpha_global_value;
1774 req->rop_code = req_rga->rop_code;
1775 req->rop_mode = req_rga->alpha_rop_mode;
1776
1777 req->color_fill_mode = req_rga->color_fill_mode;
1778 req->alpha_zero_key = req_rga->alpha_rop_mode >> 4;
1779 req->src_trans_mode = req_rga->src_trans_mode;
1780 req->color_key_min = req_rga->color_key_min;
1781 req->color_key_max = req_rga->color_key_max;
1782
1783 req->fg_color = req_rga->fg_color;
1784 req->bg_color = req_rga->bg_color;
1785 memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color));
1786 memcpy(&req->full_csc, &req_rga->full_csc, sizeof(req_rga->full_csc));
1787
1788 req->palette_mode = req_rga->palette_mode;
1789 req->yuv2rgb_mode = req_rga->yuv2rgb_mode;
1790 req->endian_mode = req_rga->endian_mode;
1791 req->rgb2yuv_mode = 0;
1792
1793 req->fading_alpha_value = 0;
1794 req->fading_r_value = req_rga->fading.r;
1795 req->fading_g_value = req_rga->fading.g;
1796 req->fading_b_value = req_rga->fading.b;
1797
1798 /* alpha mode set */
1799 req->alpha_rop_flag = 0;
1800 /* alpha_rop_enable */
1801 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag & 1)));
1802 /* rop_enable */
1803 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 1) & 1) << 1);
1804 /* fading_enable */
1805 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 2) & 1) << 2);
1806 /* alpha_cal_mode_sel */
1807 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 4) & 1) << 3);
1808 /* dst_dither_down */
1809 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6);
1810 /* gradient fill mode sel */
1811 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7);
1812 /* RGA_NN_QUANTIZE */
1813 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 8) & 1) << 8);
1814 req->dither_mode = req_rga->dither_mode;
1815
1816 if (((req_rga->alpha_rop_flag) & 1)) {
1817 if ((req_rga->alpha_rop_flag >> 3) & 1) {
1818 /* porter duff alpha enable */
1819 switch (req_rga->PD_mode) {
1820 /* dst = 0 */
1821 case 0:
1822 break;
1823 /* dst = src */
1824 case 1:
1825 req->alpha_mode_0 = 0x0212;
1826 req->alpha_mode_1 = 0x0212;
1827 break;
1828 /* dst = dst */
1829 case 2:
1830 req->alpha_mode_0 = 0x1202;
1831 req->alpha_mode_1 = 0x1202;
1832 break;
1833 /* dst = (256*sc + (256 - sa)*dc) >> 8 */
1834 case 3:
1835 if ((req_rga->alpha_rop_mode & 3) == 0) {
1836 /* both use globalAlpha. */
1837 alpha_mode_0 = 0x3010;
1838 alpha_mode_1 = 0x3010;
1839 } else if ((req_rga->alpha_rop_mode & 3) == 1) {
1840 /* Do not use globalAlpha. */
1841 alpha_mode_0 = 0x3212;
1842 alpha_mode_1 = 0x3212;
1843 } else if ((req_rga->alpha_rop_mode & 3) == 2) {
1844 /*
1845 * dst use globalAlpha,
1846 * and dst has pixelAlpha.
1847 */
1848 alpha_mode_0 = 0x3014;
1849 alpha_mode_1 = 0x3014;
1850 } else {
1851 /*
1852 * dst use globalAlpha, and
1853 * dst does not have pixelAlpha.
1854 */
1855 alpha_mode_0 = 0x3012;
1856 alpha_mode_1 = 0x3012;
1857 }
1858 req->alpha_mode_0 = alpha_mode_0;
1859 req->alpha_mode_1 = alpha_mode_1;
1860 break;
1861 /* dst = (sc*(256-da) + 256*dc) >> 8 */
1862 case 4:
1863 /* Do not use globalAlpha. */
1864 req->alpha_mode_0 = 0x1232;
1865 req->alpha_mode_1 = 0x1232;
1866 break;
1867 /* dst = (da*sc) >> 8 */
1868 case 5:
1869 break;
1870 /* dst = (sa*dc) >> 8 */
1871 case 6:
1872 break;
1873 /* dst = ((256-da)*sc) >> 8 */
1874 case 7:
1875 break;
1876 /* dst = ((256-sa)*dc) >> 8 */
1877 case 8:
1878 break;
1879 /* dst = (da*sc + (256-sa)*dc) >> 8 */
1880 case 9:
1881 req->alpha_mode_0 = 0x3040;
1882 req->alpha_mode_1 = 0x3040;
1883 break;
1884 /* dst = ((256-da)*sc + (sa*dc)) >> 8 */
1885 case 10:
1886 break;
1887 /* dst = ((256-da)*sc + (256-sa)*dc) >> 8 */
1888 case 11:
1889 break;
1890 case 12:
1891 req->alpha_mode_0 = 0x0010;
1892 req->alpha_mode_1 = 0x0820;
1893 break;
1894 default:
1895 break;
1896 }
1897 /* Real color mode */
1898 if ((req_rga->alpha_rop_flag >> 9) & 1) {
1899 if (req->alpha_mode_0 & (0x01 << 1))
1900 req->alpha_mode_0 |= (1 << 7);
1901 if (req->alpha_mode_0 & (0x01 << 9))
1902 req->alpha_mode_0 |= (1 << 15);
1903 }
1904 } else {
1905 if ((req_rga->alpha_rop_mode & 3) == 0) {
1906 req->alpha_mode_0 = 0x3040;
1907 req->alpha_mode_1 = 0x3040;
1908 } else if ((req_rga->alpha_rop_mode & 3) == 1) {
1909 req->alpha_mode_0 = 0x3042;
1910 req->alpha_mode_1 = 0x3242;
1911 } else if ((req_rga->alpha_rop_mode & 3) == 2) {
1912 req->alpha_mode_0 = 0x3044;
1913 req->alpha_mode_1 = 0x3044;
1914 }
1915 }
1916 }
1917
1918 if (req_rga->mmu_info.mmu_en && (req_rga->mmu_info.mmu_flag & 1) == 1) {
1919 req->mmu_info.src0_mmu_flag = 1;
1920 req->mmu_info.dst_mmu_flag = 1;
1921
1922 if (req_rga->mmu_info.mmu_flag >> 31) {
1923 req->mmu_info.src0_mmu_flag =
1924 ((req_rga->mmu_info.mmu_flag >> 8) & 1);
1925 req->mmu_info.src1_mmu_flag =
1926 ((req_rga->mmu_info.mmu_flag >> 9) & 1);
1927 req->mmu_info.dst_mmu_flag =
1928 ((req_rga->mmu_info.mmu_flag >> 10) & 1);
1929 req->mmu_info.els_mmu_flag =
1930 ((req_rga->mmu_info.mmu_flag >> 11) & 1);
1931 } else {
1932 if (req_rga->src.yrgb_addr >= 0xa0000000) {
1933 req->mmu_info.src0_mmu_flag = 0;
1934 req->src.yrgb_addr =
1935 req_rga->src.yrgb_addr - 0x60000000;
1936 req->src.uv_addr =
1937 req_rga->src.uv_addr - 0x60000000;
1938 req->src.v_addr =
1939 req_rga->src.v_addr - 0x60000000;
1940 }
1941
1942 if (req_rga->dst.yrgb_addr >= 0xa0000000) {
1943 req->mmu_info.dst_mmu_flag = 0;
1944 req->dst.yrgb_addr =
1945 req_rga->dst.yrgb_addr - 0x60000000;
1946 }
1947
1948 if (req_rga->pat.yrgb_addr >= 0xa0000000) {
1949 req->mmu_info.src1_mmu_flag = 0;
1950 req->src1.yrgb_addr =
1951 req_rga->pat.yrgb_addr - 0x60000000;
1952 }
1953 }
1954 }
1955 }
1956
rga2_soft_reset(struct rga_scheduler_t * rga_scheduler)1957 void rga2_soft_reset(struct rga_scheduler_t *rga_scheduler)
1958 {
1959 u32 i;
1960 u32 reg;
1961
1962 rga_write((1 << 3) | (1 << 4) | (1 << 6), RGA2_SYS_CTRL, rga_scheduler);
1963
1964 for (i = 0; i < RGA_RESET_TIMEOUT; i++) {
1965 /* RGA_SYS_CTRL */
1966 reg = rga_read(RGA2_SYS_CTRL, rga_scheduler) & 1;
1967
1968 if (reg == 0)
1969 break;
1970
1971 udelay(1);
1972 }
1973
1974 if (i == RGA_RESET_TIMEOUT)
1975 pr_err("soft reset timeout.\n");
1976 }
1977
rga2_check_param(const struct rga2_req * req)1978 static int rga2_check_param(const struct rga2_req *req)
1979 {
1980 if (!((req->render_mode == COLOR_FILL_MODE))) {
1981 if (unlikely
1982 ((req->src.act_w <= 0) || (req->src.act_w > 8192)
1983 || (req->src.act_h <= 0) || (req->src.act_h > 8192))) {
1984 pr_err("invalid src resolution act_w = %d, act_h = %d\n",
1985 req->src.act_w, req->src.act_h);
1986 return -EINVAL;
1987 }
1988 }
1989
1990 if (!((req->render_mode == COLOR_FILL_MODE))) {
1991 if (unlikely
1992 ((req->src.vir_w <= 0) || (req->src.vir_w > 8192)
1993 || (req->src.vir_h <= 0) || (req->src.vir_h > 8192))) {
1994 pr_err("invalid src resolution vir_w = %d, vir_h = %d\n",
1995 req->src.vir_w, req->src.vir_h);
1996 return -EINVAL;
1997 }
1998 }
1999
2000 /* check dst width and height */
2001 if (unlikely
2002 ((req->dst.act_w <= 0) || (req->dst.act_w > 4096)
2003 || (req->dst.act_h <= 0) || (req->dst.act_h > 4096))) {
2004 pr_err("invalid dst resolution act_w = %d, act_h = %d\n",
2005 req->dst.act_w, req->dst.act_h);
2006 return -EINVAL;
2007 }
2008
2009 if (unlikely
2010 ((req->dst.vir_w <= 0) || (req->dst.vir_w > 4096)
2011 || (req->dst.vir_h <= 0) || (req->dst.vir_h > 4096))) {
2012 pr_err("invalid dst resolution vir_w = %d, vir_h = %d\n",
2013 req->dst.vir_w, req->dst.vir_h);
2014 return -EINVAL;
2015 }
2016 //check src_vir_w
2017 if (unlikely(req->src.vir_w < req->src.act_w)) {
2018 pr_err("invalid src_vir_w act_w = %d, vir_w = %d\n",
2019 req->src.act_w, req->src.vir_w);
2020 return -EINVAL;
2021 }
2022 //check dst_vir_w
2023 if (unlikely(req->dst.vir_w < req->dst.act_w)) {
2024 if (req->rotate_mode != 1) {
2025 pr_err("invalid dst_vir_w act_h = %d, vir_h = %d\n",
2026 req->dst.act_w, req->dst.vir_w);
2027 return -EINVAL;
2028 }
2029 }
2030
2031 return 0;
2032 }
2033
rga2_is_yuv10bit_format(uint32_t format)2034 static bool rga2_is_yuv10bit_format(uint32_t format)
2035 {
2036 bool ret = false;
2037
2038 switch (format) {
2039 case RGA2_FORMAT_YCbCr_420_SP_10B:
2040 case RGA2_FORMAT_YCrCb_420_SP_10B:
2041 case RGA2_FORMAT_YCbCr_422_SP_10B:
2042 case RGA2_FORMAT_YCrCb_422_SP_10B:
2043 ret = true;
2044 break;
2045 }
2046 return ret;
2047 }
2048
rga2_is_yuv8bit_format(uint32_t format)2049 static bool rga2_is_yuv8bit_format(uint32_t format)
2050 {
2051 bool ret = false;
2052
2053 switch (format) {
2054 case RGA2_FORMAT_YCbCr_422_SP:
2055 case RGA2_FORMAT_YCbCr_422_P:
2056 case RGA2_FORMAT_YCbCr_420_SP:
2057 case RGA2_FORMAT_YCbCr_420_P:
2058 case RGA2_FORMAT_YCrCb_422_SP:
2059 case RGA2_FORMAT_YCrCb_422_P:
2060 case RGA2_FORMAT_YCrCb_420_SP:
2061 case RGA2_FORMAT_YCrCb_420_P:
2062 ret = true;
2063 break;
2064 }
2065 return ret;
2066 }
2067
rga2_align_check(struct rga2_req * req)2068 static int rga2_align_check(struct rga2_req *req)
2069 {
2070 if (rga2_is_yuv10bit_format(req->src.format))
2071 if ((req->src.vir_w % 16) || (req->src.x_offset % 2) ||
2072 (req->src.act_w % 2) || (req->src.y_offset % 2) ||
2073 (req->src.act_h % 2) || (req->src.vir_h % 2))
2074 pr_info("err src wstride, 10bit yuv\n");
2075 if (rga2_is_yuv10bit_format(req->dst.format))
2076 if ((req->dst.vir_w % 16) || (req->dst.x_offset % 2) ||
2077 (req->dst.act_w % 2) || (req->dst.y_offset % 2) ||
2078 (req->dst.act_h % 2) || (req->dst.vir_h % 2))
2079 pr_info("err dst wstride, 10bit yuv\n");
2080 if (rga2_is_yuv8bit_format(req->src.format))
2081 if ((req->src.vir_w % 8) || (req->src.x_offset % 2) ||
2082 (req->src.act_w % 2) || (req->src.y_offset % 2) ||
2083 (req->src.act_h % 2) || (req->src.vir_h % 2))
2084 pr_info("err src wstride, 8bit yuv\n");
2085 if (rga2_is_yuv8bit_format(req->dst.format))
2086 if ((req->dst.vir_w % 8) || (req->dst.x_offset % 2) ||
2087 (req->dst.act_w % 2) || (req->dst.y_offset % 2) ||
2088 (req->dst.act_h % 2) || (req->dst.vir_h % 2))
2089 pr_info("err dst wstride, 8bit yuv\n");
2090
2091 return 0;
2092 }
2093
rga2_get_render_mode_str(u8 mode)2094 static const char *rga2_get_render_mode_str(u8 mode)
2095 {
2096 switch (mode) {
2097 case 0x0:
2098 return "bitblt";
2099 case 0x1:
2100 return "RGA_COLOR_PALETTE";
2101 case 0x2:
2102 return "RGA_COLOR_FILL";
2103 case 0x3:
2104 return "update_palette_table";
2105 case 0x4:
2106 return "update_patten_buff";
2107 default:
2108 return "UNF";
2109 }
2110 }
2111
rga2_get_rotate_mode_str(u8 mode)2112 static const char *rga2_get_rotate_mode_str(u8 mode)
2113 {
2114 switch (mode) {
2115 case 0x0:
2116 return "0";
2117 case 0x1:
2118 return "90 degree";
2119 case 0x2:
2120 return "180 degree";
2121 case 0x3:
2122 return "270 degree";
2123 case 0x10:
2124 return "xmirror";
2125 case 0x20:
2126 return "ymirror";
2127 case 0x30:
2128 return "xymirror";
2129 default:
2130 return "UNF";
2131 }
2132 }
2133
rga2_get_format_name(uint32_t format)2134 static const char *rga2_get_format_name(uint32_t format)
2135 {
2136 switch (format) {
2137 case RGA2_FORMAT_RGBA_8888:
2138 return "RGBA8888";
2139 case RGA2_FORMAT_RGBX_8888:
2140 return "RGBX8888";
2141 case RGA2_FORMAT_RGB_888:
2142 return "RGB888";
2143 case RGA2_FORMAT_BGRA_8888:
2144 return "BGRA8888";
2145 case RGA2_FORMAT_BGRX_8888:
2146 return "BGRX8888";
2147 case RGA2_FORMAT_BGR_888:
2148 return "BGR888";
2149 case RGA2_FORMAT_RGB_565:
2150 return "RGB565";
2151 case RGA2_FORMAT_RGBA_5551:
2152 return "RGBA5551";
2153 case RGA2_FORMAT_RGBA_4444:
2154 return "RGBA4444";
2155 case RGA2_FORMAT_BGR_565:
2156 return "BGR565";
2157 case RGA2_FORMAT_BGRA_5551:
2158 return "BGRA5551";
2159 case RGA2_FORMAT_BGRA_4444:
2160 return "BGRA4444";
2161 case RGA2_FORMAT_ARGB_8888:
2162 return "ARGB8888";
2163 case RGA2_FORMAT_XRGB_8888:
2164 return "XBGR8888";
2165 case RGA2_FORMAT_ARGB_5551:
2166 return "ARGB5551";
2167 case RGA2_FORMAT_ARGB_4444:
2168 return "ARGB4444";
2169 case RGA2_FORMAT_ABGR_8888:
2170 return "ABGR8888";
2171 case RGA2_FORMAT_XBGR_8888:
2172 return "XBGR8888";
2173 case RGA2_FORMAT_ABGR_5551:
2174 return "ABGR5551";
2175 case RGA2_FORMAT_ABGR_4444:
2176 return "ABGR4444";
2177
2178 case RGA2_FORMAT_YCbCr_422_SP:
2179 return "YCbCr422SP";
2180 case RGA2_FORMAT_YCbCr_422_P:
2181 return "YCbCr422P";
2182 case RGA2_FORMAT_YCbCr_420_SP:
2183 return "YCbCr420SP";
2184 case RGA2_FORMAT_YCbCr_420_P:
2185 return "YCbCr420P";
2186 case RGA2_FORMAT_YCrCb_422_SP:
2187 return "YCrCb422SP";
2188 case RGA2_FORMAT_YCrCb_422_P:
2189 return "YCrCb422P";
2190 case RGA2_FORMAT_YCrCb_420_SP:
2191 return "YCrCb420SP";
2192 case RGA2_FORMAT_YCrCb_420_P:
2193 return "YCrCb420P";
2194
2195 case RGA2_FORMAT_YVYU_422:
2196 return "YVYU422";
2197 case RGA2_FORMAT_YVYU_420:
2198 return "YVYU420";
2199 case RGA2_FORMAT_VYUY_422:
2200 return "VYUY422";
2201 case RGA2_FORMAT_VYUY_420:
2202 return "VYUY420";
2203 case RGA2_FORMAT_YUYV_422:
2204 return "YUYV422";
2205 case RGA2_FORMAT_YUYV_420:
2206 return "YUYV420";
2207 case RGA2_FORMAT_UYVY_422:
2208 return "UYVY422";
2209 case RGA2_FORMAT_UYVY_420:
2210 return "UYVY420";
2211
2212 case RGA2_FORMAT_YCbCr_420_SP_10B:
2213 return "YCrCb420SP10B";
2214 case RGA2_FORMAT_YCrCb_420_SP_10B:
2215 return "YCbCr420SP10B";
2216 case RGA2_FORMAT_YCbCr_422_SP_10B:
2217 return "YCbCr422SP10B";
2218 case RGA2_FORMAT_YCrCb_422_SP_10B:
2219 return "YCrCb422SP10B";
2220 case RGA2_FORMAT_BPP_1:
2221 return "BPP1";
2222 case RGA2_FORMAT_BPP_2:
2223 return "BPP2";
2224 case RGA2_FORMAT_BPP_4:
2225 return "BPP4";
2226 case RGA2_FORMAT_BPP_8:
2227 return "BPP8";
2228 case RGA2_FORMAT_YCbCr_400:
2229 return "YCbCr400";
2230 case RGA2_FORMAT_Y4:
2231 return "y4";
2232 default:
2233 return "UNF";
2234 }
2235 }
2236
rga2_get_blend_mode_str(u16 alpha_rop_flag,u16 alpha_mode_0,u16 alpha_mode_1)2237 static const char *rga2_get_blend_mode_str(u16 alpha_rop_flag, u16 alpha_mode_0,
2238 u16 alpha_mode_1)
2239 {
2240 if (alpha_rop_flag == 0) {
2241 return "no blend";
2242 } else if (alpha_rop_flag == 0x9) {
2243 if (alpha_mode_0 == 0x381A && alpha_mode_1 == 0x381A)
2244 return "105 src + (1-src.a)*dst";
2245 else if (alpha_mode_0 == 0x483A && alpha_mode_1 == 0x483A)
2246 return "405 src.a * src + (1-src.a) * dst";
2247 else
2248 return "check reg for more imformation";
2249 } else {
2250 return "check reg for more imformation";
2251 }
2252 }
2253
print_debug_info(struct rga2_req * req)2254 static void print_debug_info(struct rga2_req *req)
2255 {
2256 pr_info("render_mode:%s,bitblit_mode=%d,rotate_mode:%s\n",
2257 rga2_get_render_mode_str(req->render_mode), req->bitblt_mode,
2258 rga2_get_rotate_mode_str(req->rotate_mode));
2259
2260 pr_info("src: y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d\n",
2261 (unsigned long)req->src.yrgb_addr,
2262 (unsigned long)req->src.uv_addr,
2263 (unsigned long)req->src.v_addr,
2264 req->src.act_w, req->src.act_h,
2265 req->src.vir_w, req->src.vir_h);
2266 pr_info("src: xoff=%d yoff=%d format=%s\n",
2267 req->src.x_offset, req->src.y_offset,
2268 rga2_get_format_name(req->src.format));
2269
2270 if (req->src1.yrgb_addr != 0 || req->src1.uv_addr != 0
2271 || req->src1.v_addr != 0) {
2272 pr_info("src1: y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d\n",
2273 (unsigned long)req->src1.yrgb_addr,
2274 (unsigned long)req->src1.uv_addr,
2275 (unsigned long)req->src1.v_addr,
2276 req->src1.act_w, req->src1.act_h,
2277 req->src1.vir_w, req->src1.vir_h);
2278 pr_info("src1: xoff=%d yoff=%d format=%s\n",
2279 req->src1.x_offset, req->src1.y_offset,
2280 rga2_get_format_name(req->src1.format));
2281 }
2282
2283 pr_info("dst: y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d\n",
2284 (unsigned long)req->dst.yrgb_addr,
2285 (unsigned long)req->dst.uv_addr,
2286 (unsigned long)req->dst.v_addr,
2287 req->dst.act_w, req->dst.act_h,
2288 req->dst.vir_w, req->dst.vir_h);
2289 pr_info("dst: xoff=%d yoff=%d format=%s\n",
2290 req->dst.x_offset, req->dst.y_offset,
2291 rga2_get_format_name(req->dst.format));
2292
2293 pr_info("mmu: src=%.2x src1=%.2x dst=%.2x els=%.2x\n",
2294 req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,
2295 req->mmu_info.dst_mmu_flag, req->mmu_info.els_mmu_flag);
2296 pr_info("alpha: flag %x mode0=%x mode1=%x\n", req->alpha_rop_flag,
2297 req->alpha_mode_0, req->alpha_mode_1);
2298 pr_info("blend mode is %s\n",
2299 rga2_get_blend_mode_str(req->alpha_rop_flag, req->alpha_mode_0,
2300 req->alpha_mode_1));
2301 pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
2302 }
2303
rga2_init_reg(struct rga_job * job)2304 int rga2_init_reg(struct rga_job *job)
2305 {
2306 struct rga2_req req;
2307 int ret = 0;
2308 struct rga2_mmu_info_t *tbuf = &rga2_mmu_info;
2309 struct rga_scheduler_t *scheduler = NULL;
2310
2311 scheduler = rga_job_get_scheduler(job->core);
2312 if (scheduler == NULL) {
2313 pr_err("failed to get scheduler, %s(%d)\n", __func__,
2314 __LINE__);
2315 ret = -EINVAL;
2316 return ret;
2317 }
2318
2319 memset(&req, 0x0, sizeof(req));
2320
2321 rga_cmd_to_rga2_cmd(&job->rga_command_base, &req);
2322
2323 /* check value if legal */
2324 ret = rga2_check_param(&req);
2325 if (ret == -EINVAL) {
2326 pr_err("req argument is inval\n");
2327 return ret;
2328 }
2329
2330 rga2_align_check(&req);
2331
2332 /* for debug */
2333 if (DEBUGGER_EN(MSG))
2334 print_debug_info(&req);
2335
2336 /* RGA2 mmu set */
2337 if ((req.mmu_info.src0_mmu_flag & 1) || (req.mmu_info.src1_mmu_flag & 1)
2338 || (req.mmu_info.dst_mmu_flag & 1)
2339 || (req.mmu_info.els_mmu_flag & 1)) {
2340 ret = rga2_set_mmu_reg_info(&job->vir_page_table, &req, job);
2341 if (ret < 0) {
2342 pr_err("%s, [%d] set mmu info error\n", __func__,
2343 __LINE__);
2344 return -EFAULT;
2345 }
2346 }
2347
2348 mutex_lock(&rga_drvdata->lock);
2349
2350 if (job->vir_page_table.MMU_len && tbuf) {
2351 if (tbuf->back + job->vir_page_table.MMU_len > 2 * tbuf->size)
2352 tbuf->back = job->vir_page_table.MMU_len + tbuf->size;
2353 else
2354 tbuf->back += job->vir_page_table.MMU_len;
2355 }
2356
2357 mutex_unlock(&rga_drvdata->lock);
2358
2359 if (rga2_gen_reg_info((uint8_t *)job->cmd_reg,
2360 (uint8_t *)job->csc_reg, &req) == -1) {
2361 pr_err("gen reg info error\n");
2362 return -EINVAL;
2363 }
2364
2365 return ret;
2366 }
2367
rga_dma_flush_range(void * pstart,void * pend,struct rga_scheduler_t * scheduler)2368 static void rga_dma_flush_range(void *pstart, void *pend,
2369 struct rga_scheduler_t *scheduler)
2370 {
2371 dma_sync_single_for_device(scheduler->dev, virt_to_phys(pstart),
2372 pend - pstart, DMA_TO_DEVICE);
2373 }
2374
rga2_dump_read_back_reg(struct rga_scheduler_t * scheduler)2375 static void rga2_dump_read_back_reg(struct rga_scheduler_t *scheduler)
2376 {
2377 int i;
2378 unsigned long flags;
2379 uint32_t cmd_reg[32] = {0};
2380 uint32_t csc_reg[12] = {0};
2381
2382 spin_lock_irqsave(&scheduler->irq_lock, flags);
2383
2384 for (i = 0; i < 32; i++)
2385 cmd_reg[i] = rga_read(0x100 + i * 4, scheduler);
2386
2387 for (i = 0; i < 12; i++)
2388 csc_reg[i] = rga_read(RGA2_CSC_COE_BASE + i * 4, scheduler);
2389
2390 spin_unlock_irqrestore(&scheduler->irq_lock, flags);
2391
2392 pr_info("CMD_READ_BACK_REG\n");
2393 for (i = 0; i < 8; i++)
2394 pr_info("i = %x : %.8x %.8x %.8x %.8x\n", i,
2395 cmd_reg[0 + i * 4], cmd_reg[1 + i * 4],
2396 cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
2397
2398 pr_info("CSC_READ_BACK_REG\n");
2399 for (i = 0; i < 3; i++)
2400 pr_info("%.8x %.8x %.8x %.8x\n",
2401 csc_reg[0 + i * 4], csc_reg[1 + i * 4],
2402 csc_reg[2 + i * 4], csc_reg[3 + i * 4]);
2403 }
2404
rga2_set_reg(struct rga_job * job,struct rga_scheduler_t * scheduler)2405 int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
2406 {
2407 ktime_t now = ktime_get();
2408 int i;
2409
2410 rga_dma_flush_range(&job->cmd_reg[0], &job->cmd_reg[32], scheduler);
2411
2412 rga_write(0x0, RGA2_SYS_CTRL, scheduler);
2413
2414 #ifndef CONFIG_ROCKCHIP_FPGA
2415 /* CMD buff */
2416 rga_write(virt_to_phys(job->cmd_reg), RGA2_CMD_BASE, scheduler);
2417 #else
2418
2419 /* slave mode */
2420 {
2421 int32_t m, *cmd;
2422
2423 cmd = job->cmd_reg;
2424 pr_info("set reg\n");
2425 for (m = 0; m <= 32; m++)
2426 rga_write(cmd[m], 0x100 + m * 4, scheduler);
2427 }
2428
2429 #endif
2430
2431 /* full csc reg */
2432 for (i = 0; i < 12; i++) {
2433 rga_write(job->csc_reg[i], RGA2_CSC_COE_BASE + i * 4,
2434 scheduler);
2435 }
2436
2437 if (DEBUGGER_EN(REG)) {
2438 int32_t *p;
2439
2440 p = job->cmd_reg;
2441 pr_info("CMD_REG\n");
2442 for (i = 0; i < 8; i++)
2443 pr_info("i = %x : %.8x %.8x %.8x %.8x\n", i,
2444 p[0 + i * 4], p[1 + i * 4],
2445 p[2 + i * 4], p[3 + i * 4]);
2446
2447 p = job->csc_reg;
2448 pr_info("CSC_REG\n");
2449 for (i = 0; i < 3; i++)
2450 pr_info("%.8x %.8x %.8x %.8x\n",
2451 p[0 + i * 4], p[1 + i * 4],
2452 p[2 + i * 4], p[3 + i * 4]);
2453 }
2454
2455 #ifndef CONFIG_ROCKCHIP_FPGA
2456 /* master mode */
2457 rga_write((0x1 << 1) | (0x1 << 2) | (0x1 << 5) | (0x1 << 6),
2458 RGA2_SYS_CTRL, scheduler);
2459 #else
2460 /* slave mode */
2461 rga_write((0x0 << 1) | (0x1 << 2) | (0x1 << 5) | (0x1 << 6),
2462 RGA2_SYS_CTRL, scheduler);
2463 #endif
2464
2465 /* All CMD finish int */
2466 rga_write(rga_read(RGA2_INT, scheduler) | (0x1 << 10) | (0x1 << 9) |
2467 (0x1 << 8), RGA2_INT, scheduler);
2468
2469 if (DEBUGGER_EN(TIME)) {
2470 pr_err("sys_ctrl = %x, int = %x, set cmd use time = %lld\n",
2471 rga_read(RGA2_SYS_CTRL, scheduler),
2472 rga_read(RGA2_INT, scheduler),
2473 ktime_to_us(ktime_sub(now, job->running_time)));
2474 }
2475
2476 job->timestamp = now;
2477 job->running_time = now;
2478
2479 rga_write(1, RGA2_CMD_CTRL, scheduler);
2480
2481 if (DEBUGGER_EN(REG))
2482 rga2_dump_read_back_reg(scheduler);
2483
2484 return 0;
2485 }
2486
rga2_get_version(struct rga_scheduler_t * scheduler)2487 int rga2_get_version(struct rga_scheduler_t *scheduler)
2488 {
2489 u32 major_version, minor_version, svn_version;
2490 u32 reg_version;
2491
2492 if (!scheduler) {
2493 pr_err("scheduler is null\n");
2494 return -EINVAL;
2495 }
2496
2497 reg_version = rga_read(RGA2_VERSION_NUM, scheduler);
2498
2499 major_version = (reg_version & RGA2_MAJOR_VERSION_MASK) >> 24;
2500 minor_version = (reg_version & RGA2_MINOR_VERSION_MASK) >> 20;
2501 svn_version = (reg_version & RGA2_SVN_VERSION_MASK);
2502
2503 /*
2504 * some old rga ip has no rga version register, so force set to 2.00
2505 */
2506 if (!major_version && !minor_version)
2507 major_version = 2;
2508
2509 snprintf(scheduler->version.str, 10, "%x.%01x.%05x", major_version,
2510 minor_version, svn_version);
2511
2512 scheduler->version.major = major_version;
2513 scheduler->version.minor = minor_version;
2514 scheduler->version.revision = svn_version;
2515
2516 return 0;
2517 }
2518