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/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/
Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x00000004},
15 {0xF03600FF, 0x00000005},
16 {0x704, 0x601E0100},
17 {0x714, 0x00000000},
18 {0x718, 0x13332333},
19 {0x714, 0x00010000},
[all …]
Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/kernel/linux/linux-6.6/include/net/
Dieee80211_radiotap.h28 * @it_version: radiotap version, always 0
53 /* version is always 0 */
54 #define PKTHDR_RADIOTAP_VERSION 0
58 IEEE80211_RADIOTAP_TSFT = 0,
97 IEEE80211_RADIOTAP_F_CFP = 0x01,
98 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
99 IEEE80211_RADIOTAP_F_WEP = 0x04,
100 IEEE80211_RADIOTAP_F_FRAG = 0x08,
101 IEEE80211_RADIOTAP_F_FCS = 0x10,
102 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgk110.c38 { 0x40415c, 1, 0x04, 0x00000000 },
39 { 0x404170, 1, 0x04, 0x00000000 },
40 { 0x4041b4, 1, 0x04, 0x00000000 },
46 { 0x405844, 1, 0x04, 0x00ffffff },
47 { 0x405850, 1, 0x04, 0x00000000 },
48 { 0x405900, 1, 0x04, 0x0000ff00 },
49 { 0x405908, 1, 0x04, 0x00000000 },
50 { 0x405928, 2, 0x04, 0x00000000 },
56 { 0x407010, 1, 0x04, 0x00000000 },
57 { 0x407040, 1, 0x04, 0x80440424 },
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgk110.c38 { 0x40415c, 1, 0x04, 0x00000000 },
39 { 0x404170, 1, 0x04, 0x00000000 },
40 { 0x4041b4, 1, 0x04, 0x00000000 },
46 { 0x405844, 1, 0x04, 0x00ffffff },
47 { 0x405850, 1, 0x04, 0x00000000 },
48 { 0x405900, 1, 0x04, 0x0000ff00 },
49 { 0x405908, 1, 0x04, 0x00000000 },
50 { 0x405928, 2, 0x04, 0x00000000 },
56 { 0x407010, 1, 0x04, 0x00000000 },
57 { 0x407040, 1, 0x04, 0x80440424 },
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_0_0_default.h28 #define regSDMA0_DEC_START_DEFAULT 0x00000000
29 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000
30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
32 #define regSDMA0_POWER_CNTL_DEFAULT 0x00000000
33 #define regSDMA0_CNTL_DEFAULT 0x00002440
34 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186
35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545
36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545
37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
[all …]
/kernel/linux/linux-5.10/arch/nds32/kernel/
Dmodule.c13 GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, in module_alloc()
14 __builtin_return_address(0)); in module_alloc()
26 return 0; in module_frob_arch_sections()
33 unsigned int tmp = 0, tmp2 = 0; in do_reloc16()
35 __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n" in do_reloc16()
37 "\twsbh\t%0, %1\n" in do_reloc16()
38 "1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap) in do_reloc16()
51 "\twsbh\t%0, %1\n" in do_reloc16()
53 "\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp), in do_reloc16()
62 unsigned int tmp = 0, tmp2 = 0; in do_reloc32()
[all …]
/kernel/linux/linux-6.6/sound/drivers/vx/
Dvx_uer.c27 rmh.Cmd[0] |= CMD_MODIFY_CLOCK_S_BIT; in vx_modify_board_clock()
39 rmh.Cmd[0] |= 1 << 0; /* reference: AUDIO 0 */ in vx_modify_board_inputs()
46 * returns 0 or 1.
56 val = (vx_inb(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
60 val = (vx_inl(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
69 * @val: bit value, 0 or 1
73 val = !!val; /* 0 or 1 */ in vx_write_one_cbit()
76 vx_outb(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
79 vx_outl(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
89 * returns the frequency of UER, or 0 if not sync,
[all …]
Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
[all …]
/kernel/linux/linux-5.10/sound/drivers/vx/
Dvx_uer.c27 rmh.Cmd[0] |= CMD_MODIFY_CLOCK_S_BIT; in vx_modify_board_clock()
39 rmh.Cmd[0] |= 1 << 0; /* reference: AUDIO 0 */ in vx_modify_board_inputs()
46 * returns 0 or 1.
56 val = (vx_inb(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
60 val = (vx_inl(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
69 * @val: bit value, 0 or 1
73 val = !!val; /* 0 or 1 */ in vx_write_one_cbit()
76 vx_outb(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
79 vx_outl(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
89 * returns the frequency of UER, or 0 if not sync,
[all …]
Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Dsnps,dw-wdt.yaml52 default: [0x0001000 0x0002000 0x0004000 0x0008000
53 0x0010000 0x0020000 0x0040000 0x0080000
54 0x0100000 0x0200000 0x0400000 0x0800000
55 0x1000000 0x2000000 0x4000000 0x8000000]
70 reg = <0xffd02000 0x1000>;
71 interrupts = <0 171 4>;
79 reg = <0xffd02000 0x1000>;
80 interrupts = <0 171 4>;
83 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
84 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/
Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/kernel/linux/linux-5.10/arch/arm/include/asm/
Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
17 #define V7M_SCB_VTOR 0x08
19 #define V7M_SCB_AIRCR 0x0c
20 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
23 #define V7M_SCB_SCR 0x10
26 #define V7M_SCB_CCR 0x14
[all …]
/kernel/linux/linux-6.6/arch/arm/include/asm/
Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
16 #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
18 #define V7M_SCB_VTOR 0x08
20 #define V7M_SCB_AIRCR 0x0c
21 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
24 #define V7M_SCB_SCR 0x10
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/
Dcs42l43-regs.h13 #define CS42L43_GEN_INT_STAT_1 0x000000C0
14 #define CS42L43_GEN_INT_MASK_1 0x000000C1
15 #define CS42L43_DEVID 0x00003000
16 #define CS42L43_REVID 0x00003004
17 #define CS42L43_RELID 0x0000300C
18 #define CS42L43_SFT_RESET 0x00003020
19 #define CS42L43_DRV_CTRL1 0x00006004
20 #define CS42L43_DRV_CTRL3 0x0000600C
21 #define CS42L43_DRV_CTRL4 0x00006010
22 #define CS42L43_DRV_CTRL_5 0x00006014
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x2/
Dinit.c57 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
59 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
63 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
65 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
69 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
72 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
75 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \ in mt76_write_mac_initvals()
78 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f)) in mt76_write_mac_initvals()
82 { MT_PBF_SYS_CTRL, 0x00080c00 }, in mt76_write_mac_initvals()
83 { MT_PBF_CFG, 0x1efebcff }, in mt76_write_mac_initvals()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt76x2/
Dinit.c86 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
88 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
92 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
94 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
98 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
101 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
104 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \ in mt76_write_mac_initvals()
107 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f)) in mt76_write_mac_initvals()
111 { MT_PBF_SYS_CTRL, 0x00080c00 }, in mt76_write_mac_initvals()
112 { MT_PBF_CFG, 0x1efebcff }, in mt76_write_mac_initvals()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/fw/api/
Drx.h14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
27 * (REPLY_RX_PHY_CMD = 0xc0)
70 * bits 0:3 - reserved
78 CSUM_RXA_RESERVED_MASK = 0x000f,
79 CSUM_RXA_MICSIZE_MASK = 0x00f0,
80 CSUM_RXA_HEADERLEN_MASK = 0x1f00,
110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/via/
Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
[all …]
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-au1x00/
Dau1100_mmc.h52 #define SD0_BASE 0xB0600000
53 #define SD1_BASE 0xB0680000
59 #define SD_TXPORT (0x0000)
60 #define SD_RXPORT (0x0004)
61 #define SD_CONFIG (0x0008)
62 #define SD_ENABLE (0x000C)
63 #define SD_CONFIG2 (0x0010)
64 #define SD_BLKSIZE (0x0014)
65 #define SD_STATUS (0x0018)
66 #define SD_DEBUG (0x001C)
[all …]

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