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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_default.h26 #define mmGRBM_CNTL_DEFAULT 0x00000018
27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
28 #define mmGRBM_STATUS2_DEFAULT 0x00000000
29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
30 #define mmGRBM_STATUS_DEFAULT 0x00000000
31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
[all …]
Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_default.h26 #define mmGRBM_CNTL_DEFAULT 0x00000018
27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
28 #define mmGRBM_STATUS2_DEFAULT 0x00000000
29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
30 #define mmGRBM_STATUS_DEFAULT 0x00000000
31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
[all …]
Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dhdmigt215.c31 const u32 ctrl = 0x40000000 * enable | in gt215_hdmi_ctrl()
32 0x1f000000 /* ??? */ | in gt215_hdmi_ctrl()
42 if (!(ctrl & 0x40000000)) { in gt215_hdmi_ctrl()
43 nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000); in gt215_hdmi_ctrl()
44 nvkm_mask(device, 0x61c53c + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
45 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
46 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
51 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
53 nvkm_wr32(device, 0x61c528 + soff, avi_infoframe.header); in gt215_hdmi_ctrl()
54 nvkm_wr32(device, 0x61c52c + soff, avi_infoframe.subpack0_low); in gt215_hdmi_ctrl()
[all …]
Dhdmig84.c31 const u32 ctrl = 0x40000000 * enable | in g84_hdmi_ctrl()
32 0x1f000000 /* ??? */ | in g84_hdmi_ctrl()
35 const u32 hoff = head * 0x800; in g84_hdmi_ctrl()
42 if (!(ctrl & 0x40000000)) { in g84_hdmi_ctrl()
43 nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000); in g84_hdmi_ctrl()
44 nvkm_mask(device, 0x61653c + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
45 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
46 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
51 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
53 nvkm_wr32(device, 0x616528 + hoff, avi_infoframe.header); in g84_hdmi_ctrl()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgt215.c38 const u32 soff = ior->id * 0x800; in gt215_sor_hda_eld()
41 for (i = 0; i < size; i++) in gt215_sor_hda_eld()
42 nvkm_wr32(device, 0x61c440 + soff, (i << 8) | data[i]); in gt215_sor_hda_eld()
43 for (; i < 0x60; i++) in gt215_sor_hda_eld()
44 nvkm_wr32(device, 0x61c440 + soff, (i << 8)); in gt215_sor_hda_eld()
45 nvkm_mask(device, 0x61c448 + soff, 0x80000002, 0x80000002); in gt215_sor_hda_eld()
52 u32 data = 0x80000000; in gt215_sor_hda_hpd()
53 u32 mask = 0x80000001; in gt215_sor_hda_hpd()
55 data |= 0x00000001; in gt215_sor_hda_hpd()
57 mask |= 0x00000002; in gt215_sor_hda_hpd()
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Dg84.c37 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_vsi()
39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); in g84_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); in g84_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); in g84_sor_hdmi_infoframe_vsi()
49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ in g84_sor_hdmi_infoframe_vsi()
50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
60 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_avi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/altera/
Daltera_msgdmahw.h19 * bit 15:0 sequence number
22 * bit 15:0 read stride
31 #define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
40 #define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
72 #define MSGDMA_DESC_TX_STRIDE (0x00010001)
73 #define MSGDMA_DESC_RX_STRIDE (0x00010001)
81 * bit 15:0 - read fill level
83 u32 resp_fill_level; /* bit 15:0 */
85 * bit 15:0 - read sequence number
92 #define MSGDMA_CSR_STAT_BUSY BIT(0)
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/kernel/linux/linux-5.10/drivers/net/ethernet/altera/
Daltera_msgdmahw.h19 * bit 15:0 sequence number
22 * bit 15:0 read stride
31 #define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
40 #define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
72 #define MSGDMA_DESC_TX_STRIDE (0x00010001)
73 #define MSGDMA_DESC_RX_STRIDE (0x00010001)
81 * bit 15:0 - read fill level
83 u32 resp_fill_level; /* bit 15:0 */
85 * bit 15:0 - read sequence number
92 #define MSGDMA_CSR_STAT_BUSY BIT(0)
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Dsdma_v4_0.c75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
[all …]
/kernel/linux/linux-6.6/sound/soc/amd/rpl/
Drpl_acp6x.h10 #define ACP_DEVICE_ID 0x15E2
11 #define ACP6x_PHY_BASE_ADDRESS 0x1240000
13 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
15 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
17 #define ACP_POWERED_ON 0
/kernel/linux/linux-6.6/drivers/media/platform/mediatek/mdp3/
Dmdp_reg_rsz.h10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgf110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgf110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
/kernel/linux/linux-5.10/sound/soc/amd/renoir/
Drn_acp3x.h11 #define ACP_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_REG_START 0x1240000
13 #define ACP_REG_END 0x1250200
15 #define ACP_DEVICE_ID 0x15E2
16 #define ACP_POWER_ON 0x00
17 #define ACP_POWER_ON_IN_PROGRESS 0x01
18 #define ACP_POWER_OFF 0x02
19 #define ACP_POWER_OFF_IN_PROGRESS 0x03
20 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
22 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
[all …]
/kernel/linux/linux-6.6/sound/soc/amd/renoir/
Drn_acp3x.h11 #define ACP_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_REG_START 0x1240000
13 #define ACP_REG_END 0x1250200
15 #define ACP_DEVICE_ID 0x15E2
16 #define ACP_POWER_ON 0x00
17 #define ACP_POWER_ON_IN_PROGRESS 0x01
18 #define ACP_POWER_OFF 0x02
19 #define ACP_POWER_OFF_IN_PROGRESS 0x03
20 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
22 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dsdma_v4_0.c74 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
75 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
[all …]
/kernel/linux/linux-6.6/sound/soc/amd/yc/
Dacp6x.h10 #define ACP_DEVICE_ID 0x15E2
11 #define ACP6x_PHY_BASE_ADDRESS 0x1240000
12 #define ACP6x_REG_START 0x1240000
13 #define ACP6x_REG_END 0x1250200
17 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
19 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
21 #define ACP_POWERED_ON 0
26 #define ACP_ERROR_MASK 0x20000000
27 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
28 #define PDM_DMA_STAT 0x10
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/kernel/linux/linux-6.6/drivers/media/pci/cx18/
Dcx18-firmware.c17 #define CX18_PROC_SOFT_RESET 0xc70010
18 #define CX18_DDR_SOFT_RESET 0xc70014
19 #define CX18_CLOCK_SELECT1 0xc71000
20 #define CX18_CLOCK_SELECT2 0xc71004
21 #define CX18_HALF_CLOCK_SELECT1 0xc71008
22 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
23 #define CX18_CLOCK_POLARITY1 0xc71010
24 #define CX18_CLOCK_POLARITY2 0xc71014
25 #define CX18_ADD_DELAY_ENABLE1 0xc71018
26 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-firmware.c17 #define CX18_PROC_SOFT_RESET 0xc70010
18 #define CX18_DDR_SOFT_RESET 0xc70014
19 #define CX18_CLOCK_SELECT1 0xc71000
20 #define CX18_CLOCK_SELECT2 0xc71004
21 #define CX18_HALF_CLOCK_SELECT1 0xc71008
22 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
23 #define CX18_CLOCK_POLARITY1 0xc71010
24 #define CX18_CLOCK_POLARITY2 0xc71014
25 #define CX18_ADD_DELAY_ENABLE1 0xc71018
26 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
[all …]
/kernel/linux/linux-6.6/arch/alpha/include/asm/
Djensen.h34 #define EISA_INTA (IDENT_ADDR + 0x100000000UL)
39 #define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL)
40 #define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL)
45 #define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL)
50 #define EISA_HAE (IDENT_ADDR + 0x1D0000000UL)
55 #define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL)
60 #define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL)
65 #define EISA_MEM (IDENT_ADDR + 0x200000000UL)
70 #define EISA_IO (IDENT_ADDR + 0x300000000UL)
84 * hae needs to be set to 0).
[all …]
/kernel/linux/linux-5.10/arch/alpha/include/asm/
Djensen.h34 #define EISA_INTA (IDENT_ADDR + 0x100000000UL)
39 #define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL)
40 #define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL)
45 #define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL)
50 #define EISA_HAE (IDENT_ADDR + 0x1D0000000UL)
55 #define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL)
60 #define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL)
65 #define EISA_MEM (IDENT_ADDR + 0x200000000UL)
70 #define EISA_IO (IDENT_ADDR + 0x300000000UL)
84 * hae needs to be set to 0).
[all …]

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