Searched +full:0 +full:x0020 (Results 1 – 25 of 1088) sorted by relevance
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | cm1_7xx.h | 23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
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| D | cm2_44xx.h | 26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
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| D | cm2_54xx.h | 22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
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| D | cm1_54xx.h | 22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
28 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
31 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
32 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
33 #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
34 #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
37 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
38 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
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| D | cm1_44xx.h | 26 #define OMAP4430_CM1_BASE 0x4a004000
32 #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM1_CKGEN_INST 0x0100
34 #define OMAP4430_CM1_MPU_INST 0x0300
35 #define OMAP4430_CM1_TESLA_INST 0x0400
36 #define OMAP4430_CM1_ABE_INST 0x0500
37 #define OMAP4430_CM1_RESTORE_INST 0x0e00
38 #define OMAP4430_CM1_INSTR_INST 0x0f00
41 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
42 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
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| D | cm2_7xx.h | 23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
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| D | prm7xx.h | 26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
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| D | prcm_mpu7xx.h | 24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
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| D | prcm_mpu54xx.h | 24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
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| /kernel/linux/linux-6.6/include/linux/mfd/wm8350/ |
| D | core.h | 27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
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| D | gpio.h | 16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
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| /kernel/linux/linux-5.10/include/linux/mfd/wm8350/ |
| D | core.h | 27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
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| D | gpio.h | 16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
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| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | wm8741.h | 18 #define WM8741_DACLLSB_ATTENUATION 0x00
19 #define WM8741_DACLMSB_ATTENUATION 0x01
20 #define WM8741_DACRLSB_ATTENUATION 0x02
21 #define WM8741_DACRMSB_ATTENUATION 0x03
22 #define WM8741_VOLUME_CONTROL 0x04
23 #define WM8741_FORMAT_CONTROL 0x05
24 #define WM8741_FILTER_CONTROL 0x06
25 #define WM8741_MODE_CONTROL_1 0x07
26 #define WM8741_MODE_CONTROL_2 0x08
27 #define WM8741_RESET 0x09
[all …]
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| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| D | wm8741.h | 18 #define WM8741_DACLLSB_ATTENUATION 0x00
19 #define WM8741_DACLMSB_ATTENUATION 0x01
20 #define WM8741_DACRLSB_ATTENUATION 0x02
21 #define WM8741_DACRMSB_ATTENUATION 0x03
22 #define WM8741_VOLUME_CONTROL 0x04
23 #define WM8741_FORMAT_CONTROL 0x05
24 #define WM8741_FILTER_CONTROL 0x06
25 #define WM8741_MODE_CONTROL_1 0x07
26 #define WM8741_MODE_CONTROL_2 0x08
27 #define WM8741_RESET 0x09
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| /kernel/linux/linux-5.10/sound/pci/oxygen/ |
| D | cm9780.h | 5 #define CM9780_JACK 0x62
6 #define CM9780_MIXER 0x64
7 #define CM9780_GPIO_SETUP 0x70
8 #define CM9780_GPIO_STATUS 0x72
11 #define CM9780_RSOE 0x0001
12 #define CM9780_CBOE 0x0002
13 #define CM9780_SSOE 0x0004
14 #define CM9780_FROE 0x0008
15 #define CM9780_HP2FMICOE 0x0010
16 #define CM9780_CB2MICOE 0x0020
[all …]
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| /kernel/linux/linux-6.6/sound/pci/oxygen/ |
| D | cm9780.h | 5 #define CM9780_JACK 0x62
6 #define CM9780_MIXER 0x64
7 #define CM9780_GPIO_SETUP 0x70
8 #define CM9780_GPIO_STATUS 0x72
11 #define CM9780_RSOE 0x0001
12 #define CM9780_CBOE 0x0002
13 #define CM9780_SSOE 0x0004
14 #define CM9780_FROE 0x0008
15 #define CM9780_HP2FMICOE 0x0010
16 #define CM9780_CB2MICOE 0x0020
[all …]
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| /kernel/linux/linux-6.6/include/sound/ |
| D | wm8903.h | 15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
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| /kernel/linux/linux-5.10/include/sound/ |
| D | wm8903.h | 15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt6779.c | 13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
21 32, 0)
28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt6779.c | 13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
21 32, 0)
28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
[all …]
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| /kernel/linux/linux-5.10/include/net/ |
| D | ieee80211_radiotap.h | 28 * @it_version: radiotap version, always 0
48 /* version is always 0 */
49 #define PKTHDR_RADIOTAP_VERSION 0
53 IEEE80211_RADIOTAP_TSFT = 0,
89 IEEE80211_RADIOTAP_F_CFP = 0x01,
90 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
91 IEEE80211_RADIOTAP_F_WEP = 0x04,
92 IEEE80211_RADIOTAP_F_FRAG = 0x08,
93 IEEE80211_RADIOTAP_F_FCS = 0x10,
94 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
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| /kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/ |
| D | mii.h | 10 #define MII_BMCR 0x00
11 #define MII_BMSR 0x01
12 #define MII_PHYSID1 0x02
13 #define MII_PHYSID2 0x03
14 #define MII_ADVERTISE 0x04
15 #define MII_LPA 0x05
16 #define MII_EXPANSION 0x06
17 #define MII_CTRL1000 0x09
18 #define MII_STAT1000 0x0a
19 #define MII_MMD_CTRL 0x0d
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | prcm_mpu7xx.h | 24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
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| D | prcm_mpu54xx.h | 24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
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