Searched +full:0 +full:x01c0f000 (Results 1 – 25 of 26) sorted by relevance
12
94 reg = <0x01c0f000 0x1000>;99 cd-gpios = <&pio 7 1 0>;
107 reg = <0x01c0f000 0x1000>;112 cd-gpios = <&pio 7 1 0>;
17 #clock-cells = <0>;24 #clock-cells = <0>;33 #size-cells = <0>;35 cpu@0 {38 reg = <0x0>;51 reg = <0x01c00000 0x30>;58 reg = <0x00010000 0x1000>;61 ranges = <0 0x00010000 0x1000>;63 otg_sram: sram-section@0 {66 reg = <0x0000 0x1000>;[all …]
72 #size-cells = <0>;74 cpu@0 {77 reg = <0>;102 #clock-cells = <0>;110 #clock-cells = <0>;126 reg = <0x01000000 0x10000>;138 reg = <0x01100000 0x100000>;139 clocks = <&display_clocks 0>,143 resets = <&display_clocks 0>;147 #size-cells = <0>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
91 #size-cells = <0>;93 cpu0: cpu@0 {96 reg = <0>;112 #clock-cells = <0>;120 #clock-cells = <0>;136 reg = <0x01c00000 0x30>;143 reg = <0x01d00000 0x80000>;146 ranges = <0 0x01d00000 0x80000>;148 ve_sram: sram-section@0 {151 reg = <0x000000 0x80000>;[all …]
87 #clock-cells = <0>;95 #clock-cells = <0>;118 reg = <0x01000000 0x10000>;129 compatible = "allwinner,sun8i-h3-de2-mixer-0";130 reg = <0x01100000 0x100000>;139 #size-cells = <0>;153 reg = <0x01c02000 0x1000>;163 reg = <0x01c0c000 0x1000>;172 #size-cells = <0>;174 tcon0_in: port@0 {[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
65 #size-cells = <0>;67 cpu0: cpu@0 {73 reg = <0x0>;82 reg = <0x1>;91 reg = <0x2>;100 reg = <0x3>;109 reg = <0x100>;118 reg = <0x101>;127 reg = <0x102>;136 reg = <0x103>;[all …]
62 #size-cells = <0>;64 cpu0: cpu@0 {71 reg = <0>;115 reg = <0x100>;126 reg = <0x101>;137 reg = <0x102>;148 reg = <0x103>;168 #clock-cells = <0>;181 #clock-cells = <0>;188 #clock-cells = <0>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;213 #clock-cells = <0>;221 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;252 #clock-cells = <0>;254 reg = <0x01c200d0 0x4>;274 reg = <0x01c02000 0x1000>;[all …]
64 #clock-cells = <0>;72 #clock-cells = <0>;82 #size-cells = <0>;84 cpu0: cpu@0 {87 reg = <0>;130 polling-delay-passive = <0>;131 polling-delay = <0>;132 thermal-sensors = <&ths 0>;143 hysteresis = <0>;161 polling-delay-passive = <0>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
70 #size-cells = <0>;72 cpu@0 {75 reg = <0>;100 #clock-cells = <0>;108 #clock-cells = <0>;124 reg = <0x01000000 0x10000>;136 reg = <0x01100000 0x100000>;137 clocks = <&display_clocks 0>,141 resets = <&display_clocks 0>;145 #size-cells = <0>;[all …]
90 #size-cells = <0>;92 cpu0: cpu@0 {95 reg = <0>;111 #clock-cells = <0>;119 #clock-cells = <0>;135 reg = <0x01c00000 0x30>;142 reg = <0x01d00000 0x80000>;145 ranges = <0 0x01d00000 0x80000>;147 ve_sram: sram-section@0 {150 reg = <0x000000 0x80000>;[all …]
86 #clock-cells = <0>;94 #clock-cells = <0>;117 reg = <0x01000000 0x10000>;128 compatible = "allwinner,sun8i-h3-de2-mixer-0";129 reg = <0x01100000 0x100000>;138 #size-cells = <0>;152 reg = <0x01c02000 0x1000>;162 reg = <0x01c0c000 0x1000>;171 #size-cells = <0>;173 tcon0_in: port@0 {[all …]
63 #clock-cells = <0>;71 #clock-cells = <0>;81 #size-cells = <0>;83 cpu0: cpu@0 {86 reg = <0>;117 polling-delay-passive = <0>;118 polling-delay = <0>;119 thermal-sensors = <&ths 0>;124 polling-delay-passive = <0>;125 polling-delay = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;216 #clock-cells = <0>;224 #clock-cells = <0>;241 #clock-cells = <0>;248 #clock-cells = <0>;255 #clock-cells = <0>;257 reg = <0x01c200d0 0x4>;277 reg = <0x01c02000 0x1000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;183 size = <0x6000000>;184 alloc-ranges = <0x40000000 0x10000000>;210 #clock-cells = <0>;217 #clock-cells = <0>;233 #clock-cells = <0>;240 #clock-cells = <0>;247 #clock-cells = <0>;[all …]
47 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;124 #clock-cells = <0>;131 #clock-cells = <0>;153 #size-cells = <0>;164 simple-audio-card,dai-link@0 {175 sound-dai = <&codec 0>;197 polling-delay-passive = <0>;198 polling-delay = <0>;[all …]
46 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;106 #clock-cells = <0>;113 #clock-cells = <0>;174 polling-delay-passive = <0>;175 polling-delay = <0>;176 thermal-sensors = <&ths 0>;221 polling-delay-passive = <0>;222 polling-delay = <0>;[all …]