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/kernel/linux/linux-6.6/include/net/
Dieee80211_radiotap.h28 * @it_version: radiotap version, always 0
53 /* version is always 0 */
54 #define PKTHDR_RADIOTAP_VERSION 0
58 IEEE80211_RADIOTAP_TSFT = 0,
97 IEEE80211_RADIOTAP_F_CFP = 0x01,
98 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
99 IEEE80211_RADIOTAP_F_WEP = 0x04,
100 IEEE80211_RADIOTAP_F_FRAG = 0x08,
101 IEEE80211_RADIOTAP_F_FCS = 0x10,
102 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/kernel/linux/linux-5.10/arch/mips/lantiq/falcon/
Dprom.c25 #define PART_MASK 0x0FFFF000
27 #define REV_MASK 0xF0000000
29 #define SREV_MASK 0x03C00000
31 #define TYPE_MASK 0x3C000000
34 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
35 #define BOOT_RVEC (BOOT_REG_BASE | 0x00)
36 #define BOOT_NVEC (BOOT_REG_BASE | 0x04)
37 #define BOOT_EVEC (BOOT_REG_BASE | 0x08)
61 sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), in ltq_soc_detect()
62 i->rev & 0x7, (i->srev & 0x3) + 1); in ltq_soc_detect()
[all …]
/kernel/linux/linux-6.6/arch/mips/lantiq/falcon/
Dprom.c25 #define PART_MASK 0x0FFFF000
27 #define REV_MASK 0xF0000000
29 #define SREV_MASK 0x03C00000
31 #define TYPE_MASK 0x3C000000
34 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
35 #define BOOT_RVEC (BOOT_REG_BASE | 0x00)
36 #define BOOT_NVEC (BOOT_REG_BASE | 0x04)
37 #define BOOT_EVEC (BOOT_REG_BASE | 0x08)
61 sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), in ltq_soc_detect()
62 i->rev & 0x7, (i->srev & 0x3) + 1); in ltq_soc_detect()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dnvidia,tegra186-hsp.txt50 - bits 23.. 0:
63 reg = <0x0 0x03c00000 0x0 0xa0000>;
/kernel/linux/linux-6.6/include/uapi/linux/
Dkfd_sysfs.h28 #define HSA_CAP_HOT_PLUGGABLE 0x00000001
29 #define HSA_CAP_ATS_PRESENT 0x00000002
30 #define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004
31 #define HSA_CAP_QUEUE_SIZE_POW2 0x00000008
32 #define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010
33 #define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020
34 #define HSA_CAP_VA_LIMIT 0x00000040
35 #define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
36 #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
38 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/
Dnvidia,tegra186-hsp.yaml34 - bits 7..0:
51 - bits 23..0:
63 pattern: "^hsp@[0-9a-f]+$"
89 - pattern: "^shared[0-7]$"
90 - pattern: "^shared[0-7]$"
91 - pattern: "^shared[0-7]$"
92 - pattern: "^shared[0-7]$"
93 - pattern: "^shared[0-7]$"
94 - pattern: "^shared[0-7]$"
95 - pattern: "^shared[0-7]$"
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dar956x_initvals.h41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
Dar956x_initvals.h41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/
Dkfd_topology.h32 #define HSA_CAP_HOT_PLUGGABLE 0x00000001
33 #define HSA_CAP_ATS_PRESENT 0x00000002
34 #define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004
35 #define HSA_CAP_QUEUE_SIZE_POW2 0x00000008
36 #define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010
37 #define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020
38 #define HSA_CAP_VA_LIMIT 0x00000040
39 #define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
40 #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
42 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmpc5121ads.dts21 nand@0 {
23 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
28 ranges = <0x0 0x0 0xfc000000 0x04000000
29 0x2 0x0 0x82000000 0x00008000>;
31 flash@0,0 {
33 reg = <0 0x0 0x4000000>;
39 protected@0 {
41 reg = <0x00000000 0x00040000>; // first sector is protected
46 reg = <0x00040000 0x03c00000>; // 60M for filesystem
50 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Dmpc5121ads.dts21 nand@0 {
23 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
28 ranges = <0x0 0x0 0xfc000000 0x04000000
29 0x2 0x0 0x82000000 0x00008000>;
31 flash@0,0 {
33 reg = <0 0x0 0x4000000>;
39 protected@0 {
41 reg = <0x00000000 0x00040000>; // first sector is protected
46 reg = <0x00040000 0x03c00000>; // 60M for filesystem
50 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
Didp.h28 #define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
29 #define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
30 #define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
31 #define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
38 #define IDP_COREVOLT_VIRT (0xf0000000)
44 #if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
59 #define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
60 #define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
61 #define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
62 #define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
[all …]
/kernel/linux/linux-6.6/arch/m68k/sun3x/
Ddvma.c29 #define IOMMU_ADDR_MASK 0x03ffe000
30 #define IOMMU_CACHE_INHIBIT 0x00000040
31 #define IOMMU_FULL_BLOCK 0x00000020
32 #define IOMMU_MODIFIED 0x00000010
33 #define IOMMU_USED 0x00000008
34 #define IOMMU_WRITE_PROTECT 0x00000004
35 #define IOMMU_DT_MASK 0x00000003
36 #define IOMMU_DT_INVALID 0x00000000
37 #define IOMMU_DT_VALID 0x00000001
38 #define IOMMU_DT_BAD 0x00000002
[all …]
/kernel/linux/linux-5.10/arch/m68k/sun3x/
Ddvma.c29 #define IOMMU_ADDR_MASK 0x03ffe000
30 #define IOMMU_CACHE_INHIBIT 0x00000040
31 #define IOMMU_FULL_BLOCK 0x00000020
32 #define IOMMU_MODIFIED 0x00000010
33 #define IOMMU_USED 0x00000008
34 #define IOMMU_WRITE_PROTECT 0x00000004
35 #define IOMMU_DT_MASK 0x00000003
36 #define IOMMU_DT_INVALID 0x00000000
37 #define IOMMU_DT_VALID 0x00000001
38 #define IOMMU_DT_BAD 0x00000002
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi14 bus@0 {
19 ranges = <0x0 0x0 0x0 0x40000000>;
23 reg = <0x00100000 0xf000>,
24 <0x0010f000 0x1000>;
30 reg = <0x03100000 0x10000>;
41 reg = <0x03460000 0x20000>;
53 reg = <0x03810000 0x10000>;
60 reg = <0x03c00000 0xa0000>;
78 reg = <0x0c150000 0x90000>;
84 * Shared interrupt 0 is routed only to AON/SPE, so
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.yaml147 reg = <0x03c00000 0xa0000>;
155 reg = <0x30000000 0x50000>;
158 ranges = <0x0 0x30000000 0x50000>;
161 reg = <0x4e000 0x1000>;
167 reg = <0x4f000 0x1000>;
191 #size-cells = <0>;
/kernel/linux/linux-5.10/arch/arm/mach-ep93xx/
Dts72xx.c71 #define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */
72 #define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */
83 bits = __raw_readb(addr) & ~0x07; in ts72xx_nand_hwcontrol()
84 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ in ts72xx_nand_hwcontrol()
86 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ in ts72xx_nand_hwcontrol()
101 return !!(__raw_readb(addr) & 0x20); in ts72xx_nand_device_ready()
110 .offset = 0,
129 .chip_offset = 0,
140 .start = 0, /* filled in later */
141 .end = 0, /* filled in later */
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-ep93xx/
Dts72xx.c70 #define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */
71 #define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */
82 bits = __raw_readb(addr) & ~0x07; in ts72xx_nand_hwcontrol()
83 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ in ts72xx_nand_hwcontrol()
85 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ in ts72xx_nand_hwcontrol()
100 return !!(__raw_readb(addr) & 0x20); in ts72xx_nand_device_ready()
109 .offset = 0,
128 .chip_offset = 0,
139 .start = 0, /* filled in later */
140 .end = 0, /* filled in later */
[all …]
/kernel/linux/linux-6.6/arch/arm/net/
Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/kernel/linux/linux-5.10/arch/arm/net/
Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/kernel/linux/linux-6.6/drivers/cpufreq/
Dspeedstep-lib.c27 #define relaxed_check 0
40 [27, 25:22] (in MSR 0x2a) */ in pentium3_get_frequency()
42 { 30, 0x01 }, in pentium3_get_frequency()
43 { 35, 0x05 }, in pentium3_get_frequency()
44 { 40, 0x02 }, in pentium3_get_frequency()
45 { 45, 0x06 }, in pentium3_get_frequency()
46 { 50, 0x00 }, in pentium3_get_frequency()
47 { 55, 0x04 }, in pentium3_get_frequency()
48 { 60, 0x0b }, in pentium3_get_frequency()
49 { 65, 0x0f }, in pentium3_get_frequency()
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
Dspeedstep-lib.c27 #define relaxed_check 0
40 [27, 25:22] (in MSR 0x2a) */ in pentium3_get_frequency()
42 { 30, 0x01 }, in pentium3_get_frequency()
43 { 35, 0x05 }, in pentium3_get_frequency()
44 { 40, 0x02 }, in pentium3_get_frequency()
45 { 45, 0x06 }, in pentium3_get_frequency()
46 { 50, 0x00 }, in pentium3_get_frequency()
47 { 55, 0x04 }, in pentium3_get_frequency()
48 { 60, 0x0b }, in pentium3_get_frequency()
49 { 65, 0x0f }, in pentium3_get_frequency()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dste-u300.dts25 reg = <0x48000000 0x03c00000>;
36 reg = <0xc0011000 0x1000>;
38 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
51 clock-type = <0>; /* Slow */
52 clock-id = <0>;
56 #clock-cells = <0>;
58 clock-type = <0>; /* Slow */
63 #clock-cells = <0>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-tcon.yaml19 const: 0
128 const: 0
130 port@0:
141 "^endpoint(@[0-9])$":
164 - port@0
390 reg = <0x01c0c000 0x1000>;
401 #clock-cells = <0>;
406 #size-cells = <0>;
408 port@0 {
410 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-tcon.yaml19 const: 0
122 port@0:
134 "^endpoint(@[0-9])$":
154 - port@0
382 reg = <0x01c0c000 0x1000>;
393 #clock-cells = <0>;
398 #size-cells = <0>;
400 port@0 {
402 #size-cells = <0>;
403 reg = <0>;
[all …]

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