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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Dhdmi.txt29 - pinctrl-0: the default pinctrl state (active)
40 - #phy-cells: Number of cells in a PHY specifier; Should be 0.
63 reg = <0x04a00000 0x2f0>;
64 interrupts = <GIC_SPI 79 0>;
80 pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
91 reg = <0x4a00400 0x60>,
92 <0x4a00500 0x100>;
93 #phy-cells = <0>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ti/
Dti,am65x-dss.yaml74 const: 0
76 port@0:
125 reg = <0x04a00000 0x1000>, /* common */
126 <0x04a02000 0x1000>, /* vidl1 */
127 <0x04a06000 0x1000>, /* vid */
128 <0x04a07000 0x1000>, /* ovr1 */
129 <0x04a08000 0x1000>, /* ovr2 */
130 <0x04a0a000 0x1000>, /* vp1 */
131 <0x04a0b000 0x1000>; /* vp2 */
143 #size-cells = <0>;
[all …]
Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
83 - description: common_s0 DSS Shared common 0
107 const: 0
109 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/ti/
Dti,am65x-dss.yaml84 port@0:
130 reg = <0x04a00000 0x1000>, /* common */
131 <0x04a02000 0x1000>, /* vidl1 */
132 <0x04a06000 0x1000>, /* vid */
133 <0x04a07000 0x1000>, /* ovr1 */
134 <0x04a08000 0x1000>, /* ovr2 */
135 <0x04a0a000 0x1000>, /* vp1 */
136 <0x04a0b000 0x1000>; /* vp2 */
148 #size-cells = <0>;
149 port@0 {
[all …]
Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
91 - description: common_s0 DSS Shared common 0
113 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
165 <0x04a50000 0x10000>, /* vid1 */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/
Dhdmi.yaml90 port@0:
101 - port@0
164 reg = <0x04a00000 0x2f0>;
176 pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
189 reg = <0x009a0000 0x50c>,
190 <0x00070000 0x6158>,
191 <0x009e0000 0xfff>;
214 pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
222 #size-cells = <0>;
224 port@0 {
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/
Dk3-am62a-mcu.dtsi11 reg = <0x00 0x04084000 0x00 0x88>;
14 pinctrl-single,function-mask = <0xffffffff>;
25 reg = <0x00 0x4800000 0x00 0x400>;
35 reg = <0x00 0x4810000 0x00 0x400>;
45 reg = <0x00 0x4820000 0x00 0x400>;
55 reg = <0x00 0x4830000 0x00 0x400>;
65 reg = <0x00 0x04a00000 0x00 0x100>;
68 clocks = <&k3_clks 149 0>;
75 reg = <0x00 0x04900000 0x00 0x100>;
78 #size-cells = <0>;
[all …]
Dk3-am64-mcu.dtsi16 reg = <0x00 0x4800000 0x00 0x400>;
26 reg = <0x00 0x4810000 0x00 0x400>;
36 reg = <0x00 0x4820000 0x00 0x400>;
46 reg = <0x00 0x4830000 0x00 0x400>;
56 reg = <0x00 0x04a00000 0x00 0x100>;
59 clocks = <&k3_clks 149 0>;
66 reg = <0x00 0x04a10000 0x00 0x100>;
69 clocks = <&k3_clks 160 0>;
76 reg = <0x00 0x04900000 0x00 0x100>;
79 #size-cells = <0>;
[all …]
Dk3-am62-mcu.dtsi11 reg = <0x00 0x04084000 0x00 0x88>;
14 pinctrl-single,function-mask = <0xffffffff>;
19 reg = <0x00 0x4100000 0x00 0x1000>;
20 ti,esm-pins = <0>, <1>, <2>, <85>;
30 reg = <0x00 0x4800000 0x00 0x400>;
40 reg = <0x00 0x4810000 0x00 0x400>;
50 reg = <0x00 0x4820000 0x00 0x400>;
60 reg = <0x00 0x4830000 0x00 0x400>;
70 reg = <0x00 0x04a00000 0x00 0x100>;
73 clocks = <&k3_clks 149 0>;
[all …]
Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/
Daldebaran_ip_offset.h35 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } },
36 { { 0, 0, 0, 0, 0, 0 } },
37 { { 0, 0, 0, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0, 0 } } } };
42 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
43 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
44 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
Dk3-j721e-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
19 #clock-cells = <0>;
21 clock-frequency = <0>;
28 reg = <0x0 0x70000000 0x0 0x800000>;
31 ranges = <0x0 0x0 0x70000000 0x800000>;
33 atf-sram@0 {
34 reg = <0x0 0x20000>;
40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
43 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
/kernel/linux/linux-5.10/drivers/clk/zte/
Dclk-zx296718.c17 #define TOP_CLK_MUX0 0x04
18 #define TOP_CLK_MUX1 0x08
19 #define TOP_CLK_MUX2 0x0c
20 #define TOP_CLK_MUX3 0x10
21 #define TOP_CLK_MUX4 0x14
22 #define TOP_CLK_MUX5 0x18
23 #define TOP_CLK_MUX6 0x1c
24 #define TOP_CLK_MUX7 0x20
25 #define TOP_CLK_MUX9 0x28
28 #define TOP_CLK_GATE0 0x34
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsm6125.dtsi23 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
[all …]
Dqcm2290.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
63 reg = <0x0 0x1>;
64 clocks = <&cpufreq_hw 0>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6375.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6115.dtsi27 #clock-cells = <0>;
32 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
44 clocks = <&cpufreq_hw 0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
62 reg = <0x0 0x1>;
63 clocks = <&cpufreq_hw 0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dqcom-apq8064.dtsi24 reg = <0x80000000 0x200000>;
29 reg = <0x8f000000 0x700000>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
42 reg = <0>;
100 reg = <0x0 0x0>;
109 coefficients = <1199 0>;
130 coefficients = <1132 0>;
151 coefficients = <1199 0>;
172 coefficients = <1132 0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/
Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
[all …]
/kernel/linux/patches/linux-4.19/hispark_taurus_patch/
Dhispark_taurus.patch2 index 1877da816..0b45060b7 100644
188 @@ -0,0 +1,240 @@
218 + #size-cells = <0>;
220 + cpu@0 {
223 + reg = <0>;
261 + opp-freq = <0 1 2 3 4>;
271 + reg = <0x80000000 0x40000000>;
309 + spidev@0 {
311 + reg = <0>;
312 + pl022,interface = <0>;
[all …]