Searched +full:0 +full:x0714 (Results 1 – 25 of 91) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx7d-pinctrl.yaml | 94 reg = <0x30330000 0x10000>;
98 <0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
99 <0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
105 reg = <0x302c0000 0x10000>;
110 <0x0008 0x0038 0x0000 0x0 0x0 0x59>,
111 <0x000C 0x003C 0x0000 0x0 0x0 0x59>;
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| /kernel/linux/linux-5.10/sound/soc/mediatek/mt2701/ |
| D | mt2701-reg.h | 12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
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| /kernel/linux/linux-6.6/sound/soc/mediatek/mt2701/ |
| D | mt2701-reg.h | 12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
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| /kernel/linux/linux-5.10/drivers/media/platform/s5p-g2d/ |
| D | g2d-regs.h | 10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/samsung/s5p-g2d/ |
| D | g2d-regs.h | 10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/qcom/camss/ |
| D | camss-csiphy-3ph-1-0.c | 3 * camss-csiphy-3ph-1-0.c
5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
18 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n))
20 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n))
22 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n))
23 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n))
24 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4
25 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5
26 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n))
27 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx7d-pinfunc.h | 14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/ |
| D | imx7d-pinfunc.h | 14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
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| /kernel/linux/linux-6.6/include/linux/mfd/mt6397/ |
| D | registers.h | 11 #define MT6397_CID 0x0100
12 #define MT6397_TOP_CKPDN 0x0102
13 #define MT6397_TOP_CKPDN_SET 0x0104
14 #define MT6397_TOP_CKPDN_CLR 0x0106
15 #define MT6397_TOP_CKPDN2 0x0108
16 #define MT6397_TOP_CKPDN2_SET 0x010A
17 #define MT6397_TOP_CKPDN2_CLR 0x010C
18 #define MT6397_TOP_GPIO_CKPDN 0x010E
19 #define MT6397_TOP_RST_CON 0x0114
20 #define MT6397_WRP_CKPDN 0x011A
[all …]
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| /kernel/linux/linux-5.10/include/linux/mfd/mt6397/ |
| D | registers.h | 11 #define MT6397_CID 0x0100
12 #define MT6397_TOP_CKPDN 0x0102
13 #define MT6397_TOP_CKPDN_SET 0x0104
14 #define MT6397_TOP_CKPDN_CLR 0x0106
15 #define MT6397_TOP_CKPDN2 0x0108
16 #define MT6397_TOP_CKPDN2_SET 0x010A
17 #define MT6397_TOP_CKPDN2_CLR 0x010C
18 #define MT6397_TOP_GPIO_CKPDN 0x010E
19 #define MT6397_TOP_RST_CON 0x0114
20 #define MT6397_WRP_CKPDN 0x011A
[all …]
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| /kernel/linux/linux-5.10/include/linux/mfd/mt6323/ |
| D | registers.h | 10 #define MT6323_CHR_CON0 0x0000
11 #define MT6323_CHR_CON1 0x0002
12 #define MT6323_CHR_CON2 0x0004
13 #define MT6323_CHR_CON3 0x0006
14 #define MT6323_CHR_CON4 0x0008
15 #define MT6323_CHR_CON5 0x000A
16 #define MT6323_CHR_CON6 0x000C
17 #define MT6323_CHR_CON7 0x000E
18 #define MT6323_CHR_CON8 0x0010
19 #define MT6323_CHR_CON9 0x0012
[all …]
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| /kernel/linux/linux-6.6/include/linux/mfd/mt6323/ |
| D | registers.h | 10 #define MT6323_CHR_CON0 0x0000
11 #define MT6323_CHR_CON1 0x0002
12 #define MT6323_CHR_CON2 0x0004
13 #define MT6323_CHR_CON3 0x0006
14 #define MT6323_CHR_CON4 0x0008
15 #define MT6323_CHR_CON5 0x000A
16 #define MT6323_CHR_CON6 0x000C
17 #define MT6323_CHR_CON7 0x000E
18 #define MT6323_CHR_CON8 0x0010
19 #define MT6323_CHR_CON9 0x0012
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-exynos5260.h | 15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk-exynos5260.h | 15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
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| /kernel/linux/linux-5.10/include/video/ |
| D | aty128.h | 13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
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| /kernel/linux/linux-6.6/include/video/ |
| D | aty128.h | 13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_scl_filters.c | 31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_scl_filters.c | 31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/zydas/zd1211rw/ |
| D | zd_chip.h | 24 CR_START = 0x9000,
28 FW_START = 0xee00,
32 E2P_START = 0xf800,
33 E2P_LEN = 0x800,
36 E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */
37 E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */
39 E2P_DATA_LEN = 0x7e, /* base 0xf817 */
40 E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */
41 E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */
53 #define ZD_CR0 CTL_REG(0x0000)
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/zydas/zd1211rw/ |
| D | zd_chip.h | 24 CR_START = 0x9000,
28 FW_START = 0xee00,
32 E2P_START = 0xf800,
33 E2P_LEN = 0x800,
36 E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */
37 E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */
39 E2P_DATA_LEN = 0x7e, /* base 0xf817 */
40 E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */
41 E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */
53 #define ZD_CR0 CTL_REG(0x0000)
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| /kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/ |
| D | Hal8723BReg.h | 28 /* 0x0000h ~ 0x00FFh System Configuration */
31 #define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */
32 #define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */
33 #define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */
34 #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */
35 #define REG_9346CR_8723B 0x000A /* 2 Byte */
36 #define REG_EE_VPD_8723B 0x000C /* 2 Byte */
37 #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */
38 #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */
39 #define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/ |
| D | Hal8723BReg.h | 30 /* 0x0000h ~ 0x00FFh System Configuration */
33 #define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */
34 #define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */
35 #define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */
36 #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */
37 #define REG_9346CR_8723B 0x000A /* 2 Byte */
38 #define REG_EE_VPD_8723B 0x000C /* 2 Byte */
39 #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */
40 #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */
41 #define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */
[all …]
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| /kernel/linux/linux-5.10/include/linux/soc/samsung/ |
| D | exynos-regs-pmu.h | 17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
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| /kernel/linux/linux-6.6/include/linux/soc/samsung/ |
| D | exynos-regs-pmu.h | 17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/r128/ |
| D | r128_drv.h | 64 #define DRIVER_PATCHLEVEL 0
187 #define R128_AUX_SC_CNTL 0x1660
188 # define R128_AUX1_SC_EN (1 << 0)
189 # define R128_AUX1_SC_MODE_OR (0 << 1)
192 # define R128_AUX2_SC_MODE_OR (0 << 3)
195 # define R128_AUX3_SC_MODE_OR (0 << 5)
197 #define R128_AUX1_SC_LEFT 0x1664
198 #define R128_AUX1_SC_RIGHT 0x1668
199 #define R128_AUX1_SC_TOP 0x166c
200 #define R128_AUX1_SC_BOTTOM 0x1670
[all …]
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