Searched +full:0 +full:x0aaf0000 (Results 1 – 6 of 6) sorted by relevance
70 reg = <0x0aaf0000 0x10000>;
17 #define VID_CTL 0x0018 #define VID_ALP 0x0419 #define VID_CLF 0x0820 #define VID_VPO 0x0C21 #define VID_VPS 0x1022 #define VID_KEY1 0x2823 #define VID_KEY2 0x2C24 #define VID_MPR0 0x3025 #define VID_MPR1 0x3426 #define VID_MPR2 0x38[all …]
36 #clock-cells = <0>;41 #clock-cells = <0>;45 #clock-cells = <0>;53 #clock-cells = <0>;62 #clock-cells = <0>;68 #size-cells = <0>;70 CPU0: cpu@0 {73 reg = <0 0>;74 clocks = <&cpufreq_hw 0>;79 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
36 #clock-cells = <0>;42 #clock-cells = <0>;49 #size-cells = <0>;51 CPU0: cpu@0 {54 reg = <0x0 0x0>;59 qcom,freq-domain = <&cpufreq_hw 0>;61 clocks = <&cpufreq_hw 0>;78 reg = <0x0 0x100>;83 qcom,freq-domain = <&cpufreq_hw 0>;85 clocks = <&cpufreq_hw 0>;[all …]
77 #clock-cells = <0>;83 #clock-cells = <0>;94 reg = <0x0 0x004cd000 0x0 0x1000>;98 reg = <0x0 0x80000000 0x0 0x600000>;103 reg = <0x0 0x80600000 0x0 0x200000>;108 reg = <0x0 0x80800000 0x0 0x60000>;113 reg = <0x0 0x80860000 0x0 0x20000>;119 reg = <0x0 0x80884000 0x0 0x10000>;124 reg = <0x0 0x808ff000 0x0 0x1000>;129 reg = <0x0 0x80900000 0x0 0x200000>;[all …]