Searched +full:0 +full:x0d060000 (Results 1 – 5 of 5) sorted by relevance
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream15 implemented in hardware, between 0 and 330 0 CSI-2 input31 1 Stream 0 output44 csi2rx: csi-bridge@0d060000 {46 reg = <0x0d060000 0x1000>;56 #size-cells = <0>;58 port@0 {59 reg = <0>;63 clock-lanes = <0>;
30 - description: pixel Clock for Stream interface 048 - description: pixel reset for Stream interface 074 port@0:90 const: 0104 Stream 0 Output port node122 - port@0137 reg = <0x0d060000 0x1000>;155 #size-cells = <0>;157 port@0 {158 reg = <0>;[all …]
20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */40 #size-cells = <0>;42 PowerPC,broadway@0 {44 reg = <0>;60 ranges = <0x0c000000 0x0c000000 0x0100000061 0x0d000000 0x0d000000 0x0080000062 0x0d800000 0x0d800000 0x00800000>;68 reg = <0x0c002000 0x100>;[all …]
27 #define ERRLOGGER_0_ID_COREID_0 0x0000000028 #define ERRLOGGER_0_ID_REVISIONID_0 0x0000000429 #define ERRLOGGER_0_FAULTEN_0 0x0000000830 #define ERRLOGGER_0_ERRVLD_0 0x0000000c31 #define ERRLOGGER_0_ERRCLR_0 0x0000001032 #define ERRLOGGER_0_ERRLOG0_0 0x0000001433 #define ERRLOGGER_0_ERRLOG1_0 0x0000001834 #define ERRLOGGER_0_RSVD_00_0 0x0000001c35 #define ERRLOGGER_0_ERRLOG3_0 0x0000002036 #define ERRLOGGER_0_ERRLOG4_0 0x00000024[all …]