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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos5250-clock.txt27 reg = <0x10010000 0x30000>;
37 reg = <0x13820000 0x100>;
38 interrupts = <0 54 0>;
Dexynos5420-clock.txt28 reg = <0x10010000 0x30000>;
38 reg = <0x13820000 0x100>;
39 interrupts = <0 54 0>;
Dexynos5410-clock.txt30 #clock-cells = <0>;
35 reg = <0x10010000 0x30000>;
46 reg = <0x12C00000 0x100>;
47 interrupts = <0 51 0>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos-clock.yaml58 reg = <0x10010000 0x30000>;
Dsamsung,exynos5410-clock.yaml58 #clock-cells = <0>;
63 reg = <0x10010000 0x30000>;
Dsamsung,exynos7885-clock.yaml168 reg = <0x10010000 0x8000>;
Dsamsung,exynos5260-clock.yaml31 - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
366 #clock-cells = <0>;
372 reg = <0x10010000 0x10000>;
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
15 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
16 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
17 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
18 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
19 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_2 0x10040002
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dsifive-serial.yaml61 reg = <0x10010000 0x1000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dsifive-serial.yaml58 reg = <0x10010000 0x1000>;
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002
15 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
16 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
17 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
18 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
19 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/input/
Dmediatek,mt6779-keypad.yaml78 reg = <0 0x10010000 0 0x1000>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/samsung/
Dsamsung,exynos-sysreg.yaml86 reg = <0x10010000 0x400>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dingenic,pinctrl.yaml18 which the pin is associated and N is an integer from 0 to 31 identifying the
30 pattern: "^pinctrl@[0-9a-f]+$"
57 const: 0
60 "^gpio@[0-9]$":
157 reg = <0x10010000 0x600>;
160 #size-cells = <0>;
162 gpio@0 {
164 reg = <0>;
167 gpio-ranges = <&pinctrl 0 0 32>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dingenic,pinctrl.yaml18 which the pin is associated and N is an integer from 0 to 31 identifying the
65 const: 0
68 "^gpio@[0-9]$":
170 reg = <0x10010000 0x600>;
173 #size-cells = <0>;
175 gpio@0 {
177 reg = <0>;
180 gpio-ranges = <&pinctrl 0 0 32>;
/kernel/linux/linux-6.6/drivers/gpu/drm/loongson/
Dlsdc_regs.h24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/mediatek/
Dmt7623n.dtsi22 reg = <0 0x13000000 0 0x200>;
29 reg = <0 0x13040000 0 0x30000>;
55 reg = <0 0x14000000 0 0x1000>;
62 reg = <0 0x14010000 0 0x1000>;
64 mediatek,larb-id = <0>;
74 reg = <0 0x16010000 0 0x1000>;
86 reg = <0 0x15001000 0 0x1000>;
99 reg = <0 0x15000000 0 0x1000>;
106 reg = <0 0x10205000 0 0x1000>;
117 reg = <0 0x15004000 0 0x1000>;
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/ingenic/
Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmt7623n.dtsi22 reg = <0 0x13000000 0 0x200>;
29 reg = <0 0x13040000 0 0x30000>;
55 reg = <0 0x14000000 0 0x1000>;
62 reg = <0 0x14010000 0 0x1000>;
64 mediatek,larb-id = <0>;
74 reg = <0 0x16010000 0 0x1000>;
86 reg = <0 0x15001000 0 0x1000>;
99 reg = <0 0x15000000 0 0x1000>;
106 reg = <0 0x10205000 0 0x1000>;
117 reg = <0 0x15004000 0 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
144 compatible = "sifive,plic-1.0.0";
145 reg = <0x0 0xc000000 0x0 0x4000000>;
149 &cpu0_intc 0xffffffff
150 &cpu1_intc 0xffffffff &cpu1_intc 9
151 &cpu2_intc 0xffffffff &cpu2_intc 9
152 &cpu3_intc 0xffffffff &cpu3_intc 9
153 &cpu4_intc 0xffffffff &cpu4_intc 9>;
[all …]

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