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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dhisilicon-femac.txt32 reg = <0x10090000 0x1000>,<0x10091300 0x200>;
35 resets = <&crg 0xec 0>,<&crg 0xec 3>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dhisilicon-femac.txt32 reg = <0x10090000 0x1000>,<0x10091300 0x200>;
35 resets = <&crg 0xec 0>,<&crg 0xec 3>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dstarfive,jh7110-tdm.yaml64 const: 0
82 reg = <0x10090000 0x1000>;
97 #sound-dai-cells = <0>;
/kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
144 compatible = "sifive,plic-1.0.0";
145 reg = <0x0 0xc000000 0x0 0x4000000>;
149 &cpu0_intc 0xffffffff
150 &cpu1_intc 0xffffffff &cpu1_intc 9
151 &cpu2_intc 0xffffffff &cpu2_intc 9
152 &cpu3_intc 0xffffffff &cpu3_intc 9
153 &cpu4_intc 0xffffffff &cpu4_intc 9>;
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
168 reg = <0x0 0xc000000 0x0 0x4000000>;
169 #address-cells = <0>;
173 <&cpu0_intc 0xffffffff>,
174 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
175 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
176 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
[all …]
Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
56 reg = <0x1>;
80 reg = <0x2>;
104 reg = <0x3>;
128 reg = <0x4>;
169 #address-cells = <0>;
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Drk3xxx.dtsi43 reg = <0x20018000 0x4000>;
44 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
55 reg = <0x2001c000 0x4000>;
56 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
68 reg = <0x20078000 0x4000>;
82 #clock-cells = <0>;
88 reg = <0x10090000 0x10000>;
99 reg = <0x10138000 0x1000>;
106 reg = <0x1013c000 0x100>;
111 reg = <0x1013c200 0x20>;
[all …]
Drk3036.dtsi33 #size-cells = <0>;
39 reg = <0xf00>;
52 reg = <0xf01>;
65 reg = <0x20078000 0x4000>;
66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
102 #clock-cells = <0>;
107 reg = <0x10080000 0x2000>;
110 ranges = <0 0x10080000 0x2000>;
112 smp-sram@0 {
114 reg = <0x00 0x10>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/rockchip/
Drk3xxx.dtsi35 #clock-cells = <0>;
41 reg = <0x10090000 0x10000>;
52 reg = <0x10104000 0x800>;
64 reg = <0x10138000 0x1000>;
71 reg = <0x1013c000 0x100>;
76 reg = <0x1013c200 0x20>;
90 reg = <0x1013c600 0x20>;
99 reg = <0x1013d000 0x1000>,
100 <0x1013c100 0x0100>;
105 reg = <0x10124000 0x400>;
[all …]
Drk3036.dtsi34 #size-cells = <0>;
40 reg = <0xf00>;
53 reg = <0xf01>;
84 #clock-cells = <0>;
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
94 smp-sram@0 {
96 reg = <0x00 0x10>;
102 reg = <0x10090000 0x10000>;
122 reg = <0x10108000 0x800>;
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
185 cpu_opp: opp-table-0 {
245 #clock-cells = <0>;
250 #clock-cells = <0>;
256 #clock-cells = <0>;
262 #clock-cells = <0>;
268 #clock-cells = <0>;
274 #clock-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/kernel/linux/patches/linux-4.19/hispark_taurus_patch/
Dhispark_taurus.patch2 index 1877da816..0b45060b7 100644
188 @@ -0,0 +1,240 @@
218 + #size-cells = <0>;
220 + cpu@0 {
223 + reg = <0>;
261 + opp-freq = <0 1 2 3 4>;
271 + reg = <0x80000000 0x40000000>;
309 + spidev@0 {
311 + reg = <0>;
312 + pl022,interface = <0>;
[all …]