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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_4_0_smn.h26 // base address: 0x10100000
27 #define smnBIFL_RAS_CENTRAL_STATUS 0x10139040
29 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
30 #define smnCPM_CONTROL 0x11180460
31 #define smnPCIE_CNTL2 0x11180070
32 #define smnPCIE_CI_CNTL 0x11180080
34 #define smnPCIE_PERF_COUNT_CNTL 0x11180200
35 #define smnPCIE_PERF_CNTL_TXCLK1 0x11180204
36 #define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208
37 #define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_4_0_smn.h26 // base address: 0x10100000
27 #define smnBIFL_RAS_CENTRAL_STATUS 0x10139040
29 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
30 #define smnCPM_CONTROL 0x11180460
31 #define smnPCIE_CNTL2 0x11180070
32 #define smnPCIE_CI_CNTL 0x11180080
34 #define smnPCIE_PERF_COUNT_CNTL 0x11180200
35 #define smnPCIE_PERF_CNTL_TXCLK1 0x11180204
36 #define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208
37 #define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Darm-realview-eb-11mp-ctrevb.dts38 reg = <0x10101000 0x1000>,
39 <0x10100100 0x100>;
43 reg = <0x10102000 0x1000>;
47 reg = <0x10100000 0x100>;
51 reg = <0x10100600 0x20>;
55 reg = <0x10100620 0x20>;
Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
40 #size-cells = <0>;
42 port@0 {
43 reg = <0>;
72 reg = <0x10000000 0x200>;
76 offset = <0x08>;
77 mask = <0x01>;
78 label = "versatile:0";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/arm/
Darm-realview-eb-11mp-ctrevb.dts38 reg = <0x10101000 0x1000>,
39 <0x10100100 0x100>;
43 reg = <0x10102000 0x1000>;
47 reg = <0x10100000 0x100>;
51 reg = <0x10100600 0x20>;
55 reg = <0x10100620 0x20>;
Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
40 #size-cells = <0>;
42 port@0 {
43 reg = <0>;
72 reg = <0x10000000 0x200>;
73 ranges = <0x0 0x10000000 0x200>;
77 led@8,0 {
79 reg = <0x08 0x04>;
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/mscc/
Dluton.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x60000000 0x20000000>;
56 reg = <0x10000000 0x2c>;
61 reg = <0x10000084 0x70>;
69 pinctrl-0 = <&uart_pins>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dstarfive,jh7110-usb.yaml68 "^usb@[0-9a-f]+$":
88 ranges = <0x0 0x10100000 0x100000>;
91 starfive,stg-syscon = <&stg_syscon 0x4>;
105 usb@0 {
107 reg = <0x0 0x10000>,
108 <0x10000 0x10000>,
109 <0x20000 0x10000>;
/kernel/linux/linux-6.6/arch/arm/mach-nomadik/
Dcpu-8815.c17 #define NOMADIK_FSMC_BASE 0x10100000 /* FSMC registers */
18 #define NOMADIK_SDRAMC_BASE 0x10110000 /* SDRAM Controller */
19 #define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
20 #define NOMADIK_MDIF_BASE 0x10120000 /* MDIF */
21 #define NOMADIK_DMA0_BASE 0x10130000 /* DMA0 Controller */
22 #define NOMADIK_IC_BASE 0x10140000 /* Vectored Irq Controller */
23 #define NOMADIK_DMA1_BASE 0x10150000 /* DMA1 Controller */
24 #define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
25 #define NOMADIK_CRYP_BASE 0x10180000 /* Crypto processor */
26 #define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-nomadik/
Dcpu-8815.c30 #define NOMADIK_FSMC_BASE 0x10100000 /* FSMC registers */
31 #define NOMADIK_SDRAMC_BASE 0x10110000 /* SDRAM Controller */
32 #define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
33 #define NOMADIK_MDIF_BASE 0x10120000 /* MDIF */
34 #define NOMADIK_DMA0_BASE 0x10130000 /* DMA0 Controller */
35 #define NOMADIK_IC_BASE 0x10140000 /* Vectored Irq Controller */
36 #define NOMADIK_DMA1_BASE 0x10150000 /* DMA1 Controller */
37 #define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
38 #define NOMADIK_CRYP_BASE 0x10180000 /* Crypto processor */
39 #define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
[all …]
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-ralink/
Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/realtek/
Drtd129x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000001f000;
9 /memreserve/ 0x000000000001f000 0x00000000000e1000;
10 /memreserve/ 0x0000000001b00000 0x00000000004be000;
26 reg = <0x1f000 0x1000>;
30 reg = <0x1ffe000 0x4000>;
34 reg = <0x10100000 0xf00000>;
47 #clock-cells = <0>;
55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
57 <0x80000000 0x80000000 0x80000000>;
61 reg = <0x98000000 0x200000>;
[all …]
Drtd139x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
25 reg = <0x2f000 0x1000>;
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
46 #clock-cells = <0>;
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
59 reg = <0x98000000 0x200000>;
62 ranges = <0x0 0x98000000 0x200000>;
[all …]
Drtd16xx.dtsi23 reg = <0x2f000 0x1000>;
27 reg = <0x1ffe000 0x4000>;
31 reg = <0x10100000 0xf00000>;
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
51 reg = <0x100>;
59 reg = <0x200>;
67 reg = <0x300>;
75 reg = <0x400>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/realtek/
Drtd129x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000001f000;
9 /memreserve/ 0x000000000001f000 0x00000000000e1000;
10 /memreserve/ 0x0000000001b00000 0x00000000004be000;
26 reg = <0x1f000 0x1000>;
30 reg = <0x1ffe000 0x4000>;
34 reg = <0x10100000 0xf00000>;
47 #clock-cells = <0>;
55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
57 <0x80000000 0x80000000 0x80000000>;
61 reg = <0x98000000 0x200000>;
[all …]
Drtd139x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
25 reg = <0x2f000 0x1000>;
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
46 #clock-cells = <0>;
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
59 reg = <0x98000000 0x200000>;
62 ranges = <0x0 0x98000000 0x200000>;
[all …]
Drtd16xx.dtsi23 reg = <0x2f000 0x1000>;
27 reg = <0x1ffe000 0x4000>;
31 reg = <0x10100000 0xf00000>;
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
51 reg = <0x100>;
59 reg = <0x200>;
67 reg = <0x300>;
75 reg = <0x400>;
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-ralink/
Drt3883.h13 #define RT3883_SDRAM_BASE 0x00000000
14 #define RT3883_SYSC_BASE 0x10000000
15 #define RT3883_TIMER_BASE 0x10000100
16 #define RT3883_INTC_BASE 0x10000200
17 #define RT3883_MEMC_BASE 0x10000300
18 #define RT3883_UART0_BASE 0x10000500
19 #define RT3883_PIO_BASE 0x10000600
20 #define RT3883_FSCC_BASE 0x10000700
21 #define RT3883_NANDC_BASE 0x10000810
22 #define RT3883_I2C_BASE 0x10000900
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8712/
Drtl871x_pwrctrl.c23 #define RTL8712_SDIO_LOCAL_BASE 0X10100000
24 #define SDIO_HCPWM (RTL8712_SDIO_LOCAL_BASE + 0x0081)
32 if (pwrpriv->rpwm_retry == 0) in r8712_set_rpwm()
52 pwrpriv->rpwm_retry = 0; in r8712_set_rpwm()
54 r8712_write8(padapter, 0x1025FE58, rpwm); in r8712_set_rpwm()
55 pwrpriv->tog += 0x80; in r8712_set_rpwm()
66 smart_ps = 0; in r8712_set_ps_mode()
92 if (pwrpriv->cpwm_tog == ((preportpwrstate->state) & 0x80)) in r8712_cpwm_int_hdl()
96 pwrpriv->cpwm = (preportpwrstate->state) & 0xf; in r8712_cpwm_int_hdl()
101 pwrpriv->cpwm_tog = (preportpwrstate->state) & 0x80; in r8712_cpwm_int_hdl()
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8712/
Drtl871x_pwrctrl.c23 #define RTL8712_SDIO_LOCAL_BASE 0X10100000
24 #define SDIO_HCPWM (RTL8712_SDIO_LOCAL_BASE + 0x0081)
32 if (pwrpriv->rpwm_retry == 0) in r8712_set_rpwm()
52 pwrpriv->rpwm_retry = 0; in r8712_set_rpwm()
54 r8712_write8(padapter, 0x1025FE58, rpwm); in r8712_set_rpwm()
55 pwrpriv->tog += 0x80; in r8712_set_rpwm()
66 smart_ps = 0; in r8712_set_ps_mode()
92 if (pwrpriv->cpwm_tog == ((preportpwrstate->state) & 0x80)) in r8712_cpwm_int_hdl()
96 pwrpriv->cpwm = (preportpwrstate->state) & 0xf; in r8712_cpwm_int_hdl()
101 pwrpriv->cpwm_tog = (preportpwrstate->state) & 0x80; in r8712_cpwm_int_hdl()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/nbif/
Dnbif_6_1_offset.h26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/nbif/
Dnbif_6_1_offset.h26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]
/kernel/linux/linux-6.6/arch/mips/ath25/
Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/kernel/linux/linux-5.10/arch/mips/ath25/
Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/kernel/linux/linux-5.10/arch/x86/pci/
Dolpc.c33 * the size of the region by writing ~0 to a base address register
38 * ~0 to a base address register.
41 static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
42 0x0, 0x0, 0x0, 0x0,
43 0x0, 0x0, 0x0, 0x0,
45 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */
46 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */
47 0x0, 0x0, 0x0, 0x28100b,
48 0x0, 0x0, 0x0, 0x0,
49 0x0, 0x0, 0x0, 0x0,
[all …]

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