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/kernel/linux/linux-5.10/Documentation/admin-guide/media/
Drkisp1.rst61 YUV4:2:2 -> YUV4:2:0). They also have cropping capability on the sink pad.
70 This is the isp entity. It is connected to the sensor on sink pad 0 and
72 the CSI-2 protocol. It has a cropping capability on sink pad 0 that is
74 Cropping on sink pad 0 defines the image region from the sensor.
110 In the following example, the sensor connected to pad 0 of 'rkisp1_isp' is
121 "media-ctl" "-d" "platform:rkisp1" "-l" "'imx219 4-0010':0 -> 'rkisp1_isp':0 [1]"
122 "media-ctl" "-d" "platform:rkisp1" "-l" "'rkisp1_isp':2 -> 'rkisp1_resizer_selfpath':0 [1]"
123 "media-ctl" "-d" "platform:rkisp1" "-l" "'rkisp1_isp':2 -> 'rkisp1_resizer_mainpath':0 [0]"
125 # set format for imx219 4-0010:0
126 "media-ctl" "-d" "platform:rkisp1" "--set-v4l2" '"imx219 4-0010":0 [fmt:SRGGB10_1X10/1640x1232]'
[all …]
/kernel/linux/linux-6.6/Documentation/admin-guide/media/
Drkisp1.rst77 YUV4:2:2 -> YUV4:2:0). They also have cropping capability on the sink pad.
86 This is the isp entity. It is connected to the sensor on sink pad 0 and
88 the CSI-2 protocol. It has a cropping capability on sink pad 0 that is
90 Cropping on sink pad 0 defines the image region from the sensor.
126 In the following example, the sensor connected to pad 0 of 'rkisp1_isp' is
137 "media-ctl" "-d" "platform:rkisp1" "-l" "'imx219 4-0010':0 -> 'rkisp1_isp':0 [1]"
138 "media-ctl" "-d" "platform:rkisp1" "-l" "'rkisp1_isp':2 -> 'rkisp1_resizer_selfpath':0 [1]"
139 "media-ctl" "-d" "platform:rkisp1" "-l" "'rkisp1_isp':2 -> 'rkisp1_resizer_mainpath':0 [0]"
141 # set format for imx219 4-0010:0
142 "media-ctl" "-d" "platform:rkisp1" "--set-v4l2" '"imx219 4-0010":0 [fmt:SRGGB10_1X10/1640x1232]'
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/kernel/liteos_a/testsuites/kernel/sample/kernel_base/ipc/event/full/
DIt_los_event_015.c50 ret = LOS_EventRead(&g_event, 0x11, LOS_WAITMODE_AND, 0); in TaskF01()
51 ICUNIT_GOTO_EQUAL(ret, 0x11, ret, EXIT); in TaskF01()
52 ICUNIT_GOTO_EQUAL(g_event.uwEventID, 0x1111, g_event.uwEventID, EXIT); in TaskF01()
55 …ret = LOS_EventRead(&g_event, 0x1100, LOS_WAITMODE_AND, 2); // 2, The timeout period for reading e… in TaskF01()
56 ICUNIT_GOTO_EQUAL(ret, 0x1100, ret, EXIT); in TaskF01()
57 ICUNIT_GOTO_EQUAL(g_event.uwEventID, 0x1111, g_event.uwEventID, EXIT); in TaskF01()
68 TSK_INIT_PARAM_S task1 = {0}; in Testcase()
76 g_testCount = 0; in Testcase()
86 LOS_EventWrite(&g_event, 0x1111); in Testcase()
93 ret = LOS_EventClear(&g_event, 0); in Testcase()
DIt_los_event_013.c46 ret = LOS_EventRead(&g_event, 0x11, LOS_WAITMODE_OR, LOS_WAIT_FOREVER); in TaskF01()
48 ICUNIT_GOTO_EQUAL(ret, 0x11, ret, EXIT); in TaskF01()
52 ret = LOS_EventRead(&g_event, 0x1100, LOS_WAITMODE_AND, 0); in TaskF01()
54 ICUNIT_GOTO_EQUAL(ret, 0x1100, ret, EXIT); in TaskF01()
55 ICUNIT_GOTO_EQUAL(g_event.uwEventID, 0x11111111, g_event.uwEventID, EXIT); in TaskF01()
59 ret = LOS_EventRead(&g_event, 0x110000, LOS_WAITMODE_AND | LOS_WAITMODE_CLR, LOS_WAIT_FOREVER); in TaskF01()
60 ICUNIT_GOTO_EQUAL(ret, 0x110000, ret, EXIT); in TaskF01()
61 ICUNIT_GOTO_EQUAL(g_event.uwEventID, 0x11001111, g_event.uwEventID, EXIT); in TaskF01()
65 ret = LOS_EventRead(&g_event, 0x11000000, LOS_WAITMODE_OR | LOS_WAITMODE_CLR, LOS_WAIT_FOREVER); in TaskF01()
66 ICUNIT_GOTO_EQUAL(ret, 0x11000000, ret, EXIT); in TaskF01()
[all …]
/kernel/liteos_m/testsuites/sample/kernel/event/
DIt_los_event_015.c46 ret = LOS_EventRead(&g_pevent, 0x11, LOS_WAITMODE_AND, 0); in TaskF01()
47 ICUNIT_GOTO_EQUAL(ret, 0x11, ret, EXIT); in TaskF01()
48 ICUNIT_GOTO_EQUAL(g_pevent.uwEventID, 0x1111, g_pevent.uwEventID, EXIT); in TaskF01()
52 …ret = LOS_EventRead(&g_pevent, 0x1100, LOS_WAITMODE_AND, 2); // 2, The timeout period for reading … in TaskF01()
53 ICUNIT_GOTO_EQUAL(ret, 0x1100, ret, EXIT); in TaskF01()
54 ICUNIT_GOTO_EQUAL(g_pevent.uwEventID, 0x1111, g_pevent.uwEventID, EXIT); in TaskF01()
67 (void)memset_s(&task1, sizeof(TSK_INIT_PARAM_S), 0, sizeof(TSK_INIT_PARAM_S)); in Testcase()
74 g_testCount = 0; in Testcase()
83 LOS_EventWrite(&g_pevent, 0x1111); in Testcase()
89 ret = LOS_EventClear(&g_pevent, 0); in Testcase()
DIt_los_event_013.c42 ret = LOS_EventRead(&g_pevent, 0x11, LOS_WAITMODE_OR, LOS_WAIT_FOREVER); in TaskF01()
44 ICUNIT_GOTO_EQUAL(ret, 0x11, ret, EXIT); in TaskF01()
48 ret = LOS_EventRead(&g_pevent, 0x1100, LOS_WAITMODE_AND, 0); in TaskF01()
50 ICUNIT_GOTO_EQUAL(ret, 0x1100, ret, EXIT); in TaskF01()
51 ICUNIT_GOTO_EQUAL(g_pevent.uwEventID, 0x11111111, g_pevent.uwEventID, EXIT); in TaskF01()
55 ret = LOS_EventRead(&g_pevent, 0x110000, LOS_WAITMODE_AND | LOS_WAITMODE_CLR, LOS_WAIT_FOREVER); in TaskF01()
56 ICUNIT_GOTO_EQUAL(ret, 0x110000, ret, EXIT); in TaskF01()
57 ICUNIT_GOTO_EQUAL(g_pevent.uwEventID, 0x11001111, g_pevent.uwEventID, EXIT); in TaskF01()
61 … ret = LOS_EventRead(&g_pevent, 0x11000000, LOS_WAITMODE_OR | LOS_WAITMODE_CLR, LOS_WAIT_FOREVER); in TaskF01()
62 ICUNIT_GOTO_EQUAL(ret, 0x11000000, ret, EXIT); in TaskF01()
[all …]
/kernel/linux/linux-5.10/arch/m68k/mac/
Dpsc.c45 for (i = 0x30 ; i < 0x70 ; i += 0x10) { in psc_debug_dump()
46 printk(KERN_DEBUG "PSC #%d: IFR = 0x%02X IER = 0x%02X\n", in psc_debug_dump()
63 for (i = 0 ; i < 9 ; i++) { in psc_dma_die_die_die()
64 psc_write_word(PSC_CTL_BASE + (i << 4), 0x8800); in psc_dma_die_die_die()
65 psc_write_word(PSC_CTL_BASE + (i << 4), 0x1000); in psc_dma_die_die_die()
66 psc_write_word(PSC_CMD_BASE + (i << 5), 0x1100); in psc_dma_die_die_die()
67 psc_write_word(PSC_CMD_BASE + (i << 5) + 0x10, 0x1100); in psc_dma_die_die_die()
105 for (i = 0x30 ; i < 0x70 ; i += 0x10) { in psc_init()
106 psc_write_byte(pIERbase + i, 0x0F); in psc_init()
107 psc_write_byte(pIFRbase + i, 0x0F); in psc_init()
[all …]
/kernel/linux/linux-6.6/arch/m68k/mac/
Dpsc.c45 for (i = 0x30 ; i < 0x70 ; i += 0x10) { in psc_debug_dump()
46 printk(KERN_DEBUG "PSC #%d: IFR = 0x%02X IER = 0x%02X\n", in psc_debug_dump()
63 for (i = 0 ; i < 9 ; i++) { in psc_dma_die_die_die()
64 psc_write_word(PSC_CTL_BASE + (i << 4), 0x8800); in psc_dma_die_die_die()
65 psc_write_word(PSC_CTL_BASE + (i << 4), 0x1000); in psc_dma_die_die_die()
66 psc_write_word(PSC_CMD_BASE + (i << 5), 0x1100); in psc_dma_die_die_die()
67 psc_write_word(PSC_CMD_BASE + (i << 5) + 0x10, 0x1100); in psc_dma_die_die_die()
105 for (i = 0x30 ; i < 0x70 ; i += 0x10) { in psc_init()
106 psc_write_byte(pIERbase + i, 0x0F); in psc_init()
107 psc_write_byte(pIFRbase + i, 0x0F); in psc_init()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
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/kernel/linux/linux-6.6/drivers/net/ethernet/apple/
Dmacmace.c39 #define N_TX_BUFF_ORDER 0
46 #define MACE_BUFF_SIZE 0x800
49 #define BROKEN_ADDRCHG_REV 0x0941
53 #define MACE_BASE (void *)(0x50F1C000)
54 #define MACE_PROM (void *)(0x50F08001)
105 psc_write_word(PSC_ENETRD_CMD + set, 0x0100); in mace_load_rxdma_base()
108 psc_write_word(PSC_ENETRD_CMD + set, 0x9800); in mace_load_rxdma_base()
109 mp->rx_tail = 0; in mace_load_rxdma_base()
124 psc_write_word(PSC_ENETRD_CTL, 0x8800); in mace_rxdma_reset()
125 mace_load_rxdma_base(dev, 0x00); in mace_rxdma_reset()
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/kernel/linux/linux-5.10/drivers/net/ethernet/apple/
Dmacmace.c39 #define N_TX_BUFF_ORDER 0
46 #define MACE_BUFF_SIZE 0x800
49 #define BROKEN_ADDRCHG_REV 0x0941
53 #define MACE_BASE (void *)(0x50F1C000)
54 #define MACE_PROM (void *)(0x50F08001)
105 psc_write_word(PSC_ENETRD_CMD + set, 0x0100); in mace_load_rxdma_base()
108 psc_write_word(PSC_ENETRD_CMD + set, 0x9800); in mace_load_rxdma_base()
109 mp->rx_tail = 0; in mace_load_rxdma_base()
124 psc_write_word(PSC_ENETRD_CTL, 0x8800); in mace_rxdma_reset()
125 mace_load_rxdma_base(dev, 0x00); in mace_rxdma_reset()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dcdns,dphy-rx.yaml21 const: 0
39 reg = <0x4580000 0x1100>;
40 #phy-cells = <0>;
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dnv40.c27 enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 };
33 case 0x43: in nv40_sensor_style()
34 case 0x44: in nv40_sensor_style()
35 case 0x4a: in nv40_sensor_style()
36 case 0x47: in nv40_sensor_style()
38 case 0x46: in nv40_sensor_style()
39 case 0x49: in nv40_sensor_style()
40 case 0x4b: in nv40_sensor_style()
41 case 0x4e: in nv40_sensor_style()
42 case 0x4c: in nv40_sensor_style()
[all …]
Dg84.c34 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) in g84_temp_get()
35 return nvkm_rd32(device, 0x20400); in g84_temp_get()
46 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) { in g84_sensor_setup()
47 nvkm_mask(device, 0x20008, 0x80008000, 0x80000000); in g84_sensor_setup()
48 nvkm_mask(device, 0x2000c, 0x80000003, 0x00000000); in g84_sensor_setup()
63 /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */ in g84_therm_program_alarms()
64 nvkm_wr32(device, 0x20000, 0x000003ff); in g84_therm_program_alarms()
67 nvkm_wr32(device, 0x20484, sensor->thrs_shutdown.hysteresis); in g84_therm_program_alarms()
68 nvkm_wr32(device, 0x20480, sensor->thrs_shutdown.temp); in g84_therm_program_alarms()
71 nvkm_wr32(device, 0x204c4, sensor->thrs_fan_boost.temp); in g84_therm_program_alarms()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dnv40.c27 enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 };
33 case 0x43: in nv40_sensor_style()
34 case 0x44: in nv40_sensor_style()
35 case 0x4a: in nv40_sensor_style()
36 case 0x47: in nv40_sensor_style()
38 case 0x46: in nv40_sensor_style()
39 case 0x49: in nv40_sensor_style()
40 case 0x4b: in nv40_sensor_style()
41 case 0x4e: in nv40_sensor_style()
42 case 0x4c: in nv40_sensor_style()
[all …]
Dg84.c34 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) in g84_temp_get()
35 return nvkm_rd32(device, 0x20400); in g84_temp_get()
46 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) { in g84_sensor_setup()
47 nvkm_mask(device, 0x20008, 0x80008000, 0x80000000); in g84_sensor_setup()
48 nvkm_mask(device, 0x2000c, 0x80000003, 0x00000000); in g84_sensor_setup()
63 /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */ in g84_therm_program_alarms()
64 nvkm_wr32(device, 0x20000, 0x000003ff); in g84_therm_program_alarms()
67 nvkm_wr32(device, 0x20484, sensor->thrs_shutdown.hysteresis); in g84_therm_program_alarms()
68 nvkm_wr32(device, 0x20480, sensor->thrs_shutdown.temp); in g84_therm_program_alarms()
71 nvkm_wr32(device, 0x204c4, sensor->thrs_fan_boost.temp); in g84_therm_program_alarms()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/
Dqcom,usb-vbus-regulator.yaml35 #size-cells = <0>;
38 reg = <0x1100>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
61 reg = <0 0x1100>;
69 reg = <0 0x40353000 0 0x3000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/sprd/
Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
61 reg = <0 0x1100>;
69 reg = <0 0x40353000 0 0x3000>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/
Dqcom,usb-vbus-regulator.yaml41 #size-cells = <0>;
44 reg = <0x1100>;
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
/kernel/linux/linux-5.10/arch/sparc/include/asm/
Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/kernel/linux/linux-6.6/arch/sparc/include/asm/
Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]

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