Searched +full:0 +full:x114 (Results 1 – 25 of 675) sorted by relevance
12345678910>>...27
| /kernel/linux/linux-5.10/include/linux/mfd/syscon/ |
| D | atmel-matrix.h | 11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
|
| /kernel/linux/linux-6.6/include/linux/mfd/syscon/ |
| D | atmel-matrix.h | 11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.h | 10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/usb/stk1160/ |
| D | stk1160-reg.h | 14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/usb/stk1160/ |
| D | stk1160-reg.h | 14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
|
| /kernel/linux/linux-5.10/drivers/reset/ |
| D | reset-uniphier.c | 20 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
45 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
46 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
51 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
52 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
53 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
54 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
55 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
56 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
57 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
|
| /kernel/linux/linux-6.6/drivers/reset/ |
| D | reset-uniphier.c | 19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
55 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
|
| D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
|
| D | phy-qcom-qmp-qserdes-ln-shrd-v6.h | 9 #define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
10 #define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
11 #define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
12 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
13 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
14 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
15 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
16 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
17 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
18 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | nxp,lpc3220-clk.txt | 18 ranges = <0x0 0x040004000 0x00001000>;
22 clk: clock-controller@0 {
24 reg = <0x00 0x114>;
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | nxp,lpc3220-clk.txt | 18 ranges = <0x0 0x040004000 0x00001000>;
22 clk: clock-controller@0 {
24 reg = <0x00 0x114>;
|
| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci_f_sdh30.h | 11 #define F_SDH30_AHB_CONFIG 0x100
18 #define F_SDH30_AHB_INCR_4 BIT(0)
20 #define F_SDH30_TUNING_SETTING 0x108
23 #define F_SDH30_IO_CONTROL2 0x114
27 #define F_SDH30_ESD_CONTROL 0x124
|
| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | sdhci_f_sdh30.h | 11 #define F_SDH30_AHB_CONFIG 0x100
18 #define F_SDH30_AHB_INCR_4 BIT(0)
20 #define F_SDH30_TUNING_SETTING 0x108
23 #define F_SDH30_IO_CONTROL2 0x114
27 #define F_SDH30_ESD_CONTROL 0x124
32 #define F_SDH30_TEST 0x158
|
| /kernel/linux/linux-6.6/drivers/media/rc/keymaps/ |
| D | rc-minix-neo.c | 14 { 0x118, KEY_POWER },
16 { 0x146, KEY_UP },
17 { 0x116, KEY_DOWN },
18 { 0x147, KEY_LEFT },
19 { 0x115, KEY_RIGHT },
20 { 0x155, KEY_ENTER },
22 { 0x110, KEY_VOLUMEDOWN },
23 { 0x140, KEY_BACK },
24 { 0x114, KEY_VOLUMEUP },
26 { 0x10d, KEY_HOME },
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | atmel_pdc.h | 15 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
17 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
18 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
19 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
20 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
21 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
22 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | atmel_pdc.h | 15 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
17 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
18 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
19 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
20 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
21 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
22 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]
|
| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | wm8505fb_regs.h | 15 * Color space select register, default value 0x1c
22 #define WMT_GOVR_COLORSPACE 0x1e4
28 #define WMT_GOVR_COLORSPACE1 0x30
30 #define WMT_GOVR_CONTRAST 0x1b8
31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
34 #define WMT_GOVR_FBADDR 0x90
35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
38 #define WMT_GOVR_XPAN 0xa4
39 #define WMT_GOVR_YPAN 0xa0
41 #define WMT_GOVR_XRES 0x98
[all …]
|
| /kernel/linux/linux-6.6/drivers/video/fbdev/ |
| D | wm8505fb_regs.h | 15 * Color space select register, default value 0x1c
22 #define WMT_GOVR_COLORSPACE 0x1e4
28 #define WMT_GOVR_COLORSPACE1 0x30
30 #define WMT_GOVR_CONTRAST 0x1b8
31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
34 #define WMT_GOVR_FBADDR 0x90
35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
38 #define WMT_GOVR_XPAN 0xa4
39 #define WMT_GOVR_YPAN 0xa0
41 #define WMT_GOVR_XRES 0x98
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/usb/gspca/ |
| D | stk1135.h | 8 #define STK1135_REG_GCTRL 0x000 /* GPIO control */
9 #define STK1135_REG_ICTRL 0x004 /* Interrupt control */
10 #define STK1135_REG_IDATA 0x008 /* Interrupt data */
11 #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */
12 #define STK1135_REG_POSVA 0x010 /* Power-on strapping data */
14 #define STK1135_REG_SENSO 0x018 /* Sensor select options */
15 #define STK1135_REG_PLLFD 0x01c /* PLL frequency divider */
17 #define STK1135_REG_SCTRL 0x100 /* Sensor control register */
18 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */
19 #define STK1135_REG_CISPO 0x110 /* Capture image starting position */
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/usb/gspca/ |
| D | stk1135.h | 8 #define STK1135_REG_GCTRL 0x000 /* GPIO control */
9 #define STK1135_REG_ICTRL 0x004 /* Interrupt control */
10 #define STK1135_REG_IDATA 0x008 /* Interrupt data */
11 #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */
12 #define STK1135_REG_POSVA 0x010 /* Power-on strapping data */
14 #define STK1135_REG_SENSO 0x018 /* Sensor select options */
15 #define STK1135_REG_PLLFD 0x01c /* PLL frequency divider */
17 #define STK1135_REG_SCTRL 0x100 /* Sensor control register */
18 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */
19 #define STK1135_REG_CISPO 0x110 /* Capture image starting position */
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-davinci/ |
| D | clock.h | 13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-davinci/ |
| D | clock.h | 13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
|
| /kernel/linux/linux-5.10/arch/sh/drivers/pci/ |
| D | pci-sh7780.h | 13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
|
| /kernel/linux/linux-6.6/arch/sh/drivers/pci/ |
| D | pci-sh7780.h | 13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
|
12345678910>>...27