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/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-at91.h12 #define PIO_PER 0x00 /* Enable Register */
13 #define PIO_PDR 0x04 /* Disable Register */
14 #define PIO_PSR 0x08 /* Status Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
16 #define PIO_ODR 0x14 /* Output Disable Register */
17 #define PIO_OSR 0x18 /* Output Status Register */
18 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
19 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
20 #define PIO_IFSR 0x28 /* Glitch Input Filter Status */
21 #define PIO_SODR 0x30 /* Set Output Data Register */
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-at91.h12 #define PIO_PER 0x00 /* Enable Register */
13 #define PIO_PDR 0x04 /* Disable Register */
14 #define PIO_PSR 0x08 /* Status Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
16 #define PIO_ODR 0x14 /* Output Disable Register */
17 #define PIO_OSR 0x18 /* Output Status Register */
18 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
19 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
20 #define PIO_IFSR 0x28 /* Glitch Input Filter Status */
21 #define PIO_SODR 0x30 /* Set Output Data Register */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-single.txt32 pinctrl-single,power-source = <0x30 0xf0>;
38 pinctrl-single,bias-pullup = <0 1 0 1>;
44 pinctrl-single,bias-pulldown = <2 2 0 2>;
61 pinctrl-single,input-schmitt = <0x30 0x70>;
67 pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
74 pinctrl-single,low-power-mode = <0x288 0x388>;
83 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
102 pinctrl-single,pins = <0xdc 0x118>;
104 Where 0xdc is the offset from the pinctrl register base address for the device
105 pinctrl register, and 0x118 contains the desired value of the pinctrl register.
[all …]
/kernel/linux/linux-5.10/drivers/crypto/
Datmel-tdes-regs.h5 #define TDES_CR 0x00
6 #define TDES_CR_START (1 << 0)
10 #define TDES_MR 0x04
11 #define TDES_MR_CYPHER_DEC (0 << 0)
12 #define TDES_MR_CYPHER_ENC (1 << 0)
13 #define TDES_MR_TDESMOD_MASK (0x3 << 1)
14 #define TDES_MR_TDESMOD_DES (0x0 << 1)
15 #define TDES_MR_TDESMOD_TDES (0x1 << 1)
16 #define TDES_MR_TDESMOD_XTEA (0x2 << 1)
17 #define TDES_MR_KEYMOD_3KEY (0 << 4)
[all …]
/kernel/linux/linux-6.6/drivers/crypto/
Datmel-tdes-regs.h5 #define TDES_CR 0x00
6 #define TDES_CR_START (1 << 0)
10 #define TDES_MR 0x04
11 #define TDES_MR_CYPHER_DEC (0 << 0)
12 #define TDES_MR_CYPHER_ENC (1 << 0)
13 #define TDES_MR_TDESMOD_MASK (0x3 << 1)
14 #define TDES_MR_TDESMOD_DES (0x0 << 1)
15 #define TDES_MR_TDESMOD_TDES (0x1 << 1)
16 #define TDES_MR_TDESMOD_XTEA (0x2 << 1)
17 #define TDES_MR_KEYMOD_3KEY (0 << 4)
[all …]
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-com.h10 #define QSERDES_COM_ATB_SEL1 0x000
11 #define QSERDES_COM_ATB_SEL2 0x004
12 #define QSERDES_COM_FREQ_UPDATE 0x008
13 #define QSERDES_COM_BG_TIMER 0x00c
14 #define QSERDES_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_COM_SSC_PER1 0x01c
18 #define QSERDES_COM_SSC_PER2 0x020
19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/syscon/
Datmel-matrix.h11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/syscon/
Datmel-matrix.h11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/falcon/
Dga102.c30 return !!(nvkm_falcon_rd32(falcon, 0x118) & 0x00000002); in ga102_flcn_dma_done()
36 nvkm_falcon_wr32(falcon, 0x114, mem_base); in ga102_flcn_dma_xfer()
37 nvkm_falcon_wr32(falcon, 0x11c, dma_base); in ga102_flcn_dma_xfer()
38 nvkm_falcon_wr32(falcon, 0x118, cmd); in ga102_flcn_dma_xfer()
47 *cmd |= 0x00000010; in ga102_flcn_dma_init()
49 *cmd |= 0x00000004; in ga102_flcn_dma_init()
51 nvkm_falcon_wr32(falcon, 0x110, dma_addr >> 8); in ga102_flcn_dma_init()
52 nvkm_falcon_wr32(falcon, 0x128, 0x00000000); in ga102_flcn_dma_init()
53 return 0; in ga102_flcn_dma_init()
66 nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000); in ga102_flcn_reset_wait_mem_scrubbing()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/b43/
Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm21664.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 secondary-boot-reg = <0x35004178>;
41 #address-cells = <0>;
43 reg = <0x3ff01000 0x1000>,
44 <0x3ff00100 0x100>;
49 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
54 reg = <0x3e000000 0x118>;
64 reg = <0x3e001000 0x118>;
[all …]
Dbcm23550.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
60 secondary-boot-reg = <0x35004178>;
69 secondary-boot-reg = <0x35004178>;
78 secondary-boot-reg = <0x35004178>;
87 ranges = <0 0x34000000 0x102f83ac>;
93 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
98 reg = <0x01001f00 0x24>;
103 reg = <0x01003000 0x524>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm21664.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
44 secondary-boot-reg = <0x35004178>;
52 #address-cells = <0>;
54 reg = <0x3ff01000 0x1000>,
55 <0x3ff00100 0x100>;
60 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
66 reg = <0x3e000000 0x118>;
76 reg = <0x3e001000 0x118>;
[all …]
Dbcm23550.dtsi48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0>;
61 secondary-boot-reg = <0x35004178>;
70 secondary-boot-reg = <0x35004178>;
79 secondary-boot-reg = <0x35004178>;
88 ranges = <0 0x34000000 0x102f83ac>;
94 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
99 reg = <0x01001f00 0x24>;
104 reg = <0x01003000 0x524>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-single.yaml48 const: 0
99 '-pins(-[0-9]+)?$|-pin$':
186 reg = <0x4a100040 0x0196>;
188 #size-cells = <0>;
193 pinctrl-single,function-mask = <0xffff>;
194 pinctrl-single,gpio-range = <&range 0 3 0>;
201 <0xd8 0x118>,
202 <0xda 0>,
203 <0xdc 0x118>,
204 <0xde 0>;
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dcpu.c20 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118); in s3c64xx_init_cpu()
26 writel_relaxed(0x0, S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
27 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
30 pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id); in s3c64xx_init_cpu()
/kernel/linux/linux-6.6/drivers/tty/serial/8250/
D8250_exar_st16c554.c16 SERIAL8250_PORT(0x100, 5),
17 SERIAL8250_PORT(0x108, 5),
18 SERIAL8250_PORT(0x110, 5),
19 SERIAL8250_PORT(0x118, 5),
/kernel/linux/linux-5.10/drivers/tty/serial/8250/
D8250_exar_st16c554.c16 SERIAL8250_PORT(0x100, 5),
17 SERIAL8250_PORT(0x108, 5),
18 SERIAL8250_PORT(0x110, 5),
19 SERIAL8250_PORT(0x118, 5),
/kernel/linux/linux-6.6/arch/arm/mach-s3c/
Dcpu.c20 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118); in s3c64xx_init_cpu()
26 writel_relaxed(0x0, S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
27 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
30 pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id); in s3c64xx_init_cpu()
/kernel/linux/linux-6.6/drivers/media/rc/keymaps/
Drc-minix-neo.c14 { 0x118, KEY_POWER },
16 { 0x146, KEY_UP },
17 { 0x116, KEY_DOWN },
18 { 0x147, KEY_LEFT },
19 { 0x115, KEY_RIGHT },
20 { 0x155, KEY_ENTER },
22 { 0x110, KEY_VOLUMEDOWN },
23 { 0x140, KEY_BACK },
24 { 0x114, KEY_VOLUMEUP },
26 { 0x10d, KEY_HOME },
[all …]
/kernel/linux/linux-5.10/include/linux/
Datmel_pdc.h15 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
17 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
18 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
19 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
20 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
21 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
22 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]
/kernel/linux/linux-6.6/include/linux/
Datmel_pdc.h15 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
17 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
18 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
19 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
20 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
21 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
22 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]

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