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/kernel/linux/linux-6.6/drivers/net/ipa/reg/
Dgsi_reg-v5.0.c12 0x0000c01c + 0x1000 * GSI_EE_AP);
15 0x0000c028 + 0x1000 * GSI_EE_AP);
18 [CHTYPE_PROTOCOL] = GENMASK(6, 0),
27 0x00014000 + 0x12000 * GSI_EE_AP, 0x80);
30 [CH_R_LENGTH] = GENMASK(23, 0),
35 0x00014004 + 0x12000 * GSI_EE_AP, 0x80);
37 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x00014008 + 0x12000 * GSI_EE_AP, 0x80);
39 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001400c + 0x12000 * GSI_EE_AP, 0x80);
42 [WRR_WEIGHT] = GENMASK(3, 0),
54 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x00014048 + 0x12000 * GSI_EE_AP, 0x80);
[all …]
/kernel/linux/linux-6.6/drivers/clk/qcom/
Dlpasscc-sdm845.c19 .halt_reg = 0x12000,
22 .enable_reg = 0x12000,
23 .enable_mask = BIT(0),
32 .halt_reg = 0x1f000,
35 .enable_reg = 0x1f000,
36 .enable_mask = BIT(0),
45 .halt_reg = 0x20,
49 .enable_reg = 0x20,
50 .enable_mask = BIT(0),
59 .halt_reg = 0x38,
[all …]
Dlpasscc-sc8280xp.c21 [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
22 [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
23 [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
31 .max_register = 0x1000,
41 [LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 },
49 .max_register = 0x12000,
74 return qcom_cc_probe_by_index(pdev, 0, desc); in lpasscc_sc8280xp_probe()
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dlpasscc-sdm845.c18 .halt_reg = 0x12000,
21 .enable_reg = 0x12000,
22 .enable_mask = BIT(0),
31 .halt_reg = 0x1f000,
34 .enable_reg = 0x1f000,
35 .enable_mask = BIT(0),
44 .halt_reg = 0x20,
48 .enable_reg = 0x20,
49 .enable_mask = BIT(0),
58 .halt_reg = 0x38,
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/ast/
Dast_dp501.c34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/ast/
Dast_dp501.c34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-dove/
Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-dove/
Ddove.h19 * e0000000 @runtime 128M PCIe-0 Memory space
23 * f2000000 fee00000 1M PCIe-0 I/O space
27 #define DOVE_CESA_PHYS_BASE 0xc8000000
28 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
31 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
34 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
37 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
40 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
44 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-dove/include/mach/
Duncompress.h7 #define UART0_PHYS_BASE (0xf1000000 + 0x12000)
9 #define UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
10 #define UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
12 #define LSR_THRE 0x20
18 for (i = 0; i < 0x1000; i++) { in putc()
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dlpc4350.dtsi18 cpu@0 {
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/lpc/
Dlpc4350.dtsi18 cpu@0 {
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dqcom,sc8280xp-lpasscc.yaml47 reg = <0x032a9000 0x1000>;
56 reg = <0x033e0000 0x12000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dmvebu-uart.txt36 reg = <0x12000 0x200>;
47 reg = <0x12200 0x30>;
/kernel/linux/linux-6.6/arch/arm/mach-footbridge/include/mach/
Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dmvebu-uart.txt39 reg = <0x12000 0x18>;
40 clocks = <&uartclk 0>;
50 reg = <0x12200 0x30>;
/kernel/linux/linux-5.10/arch/arm/mach-ixp4xx/include/mach/
Dixp4xx-regs.h23 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
25 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
27 * 0x50000000 0x10000000 ioremap'd EXP BUS
29 * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
31 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG
33 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG
35 * 0x60000000 0x00004000 0xFEF15000 QMgr
41 #define IXP4XX_QMGR_BASE_PHYS 0x60000000
47 #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
48 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-footbridge/include/mach/
Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
30 #define XBUS_SIZE 0x00100000
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/xlr/
Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/qcom/venus/
Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_BASE_V6 0xa0000
24 #define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/qcom/venus/
Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
23 #define CPU_CS_A2HSOFTINTCLR 0x1c
25 #define VIDC_CTRL_INIT 0x48
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm63146.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
75 #clock-cells = <0>;
89 ranges = <0x0 0x0 0x81000000 0x8000>;
95 reg = <0x1000 0x1000>,
96 <0x2000 0x2000>,
[all …]
/kernel/linux/linux-6.6/drivers/reset/
Dreset-qcom-aoss.c30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-qcom-aoss.c30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm63178.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
100 ranges = <0 0x81000000 0x8000>;
107 reg = <0x1000 0x1000>,
[all …]
Dbcm6878.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
90 ranges = <0 0x81000000 0x8000>;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000>,
[all …]

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