| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_cfg.c | 22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_cfg.c | 22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-imx/ |
| D | mx3x.h | 36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | mx3x.h | 36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/marvell/ |
| D | armada-37xx.txt | 16 reg = <0x14000 0x60>;
31 reg = <0x11500 0x40>;
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | mpc512x-dma.txt | 24 reg = <0x14000 0x1800>;
25 interrupts = <65 0x8>;
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | mpc512x-dma.txt | 24 reg = <0x14000 0x1800>;
25 interrupts = <65 0x8>;
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | apple,nco.yaml | 53 #clock-cells = <0>;
60 reg = <0x3b044000 0x14000>;
|
| /kernel/linux/linux-5.10/arch/arm/mach-mmp/ |
| D | regs-timers.h | 11 #define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
12 #define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
14 #define TMR_CCR (0x0000)
15 #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
16 #define TMR_CR(n) (0x0028 + ((n) << 2))
17 #define TMR_SR(n) (0x0034 + ((n) << 2))
18 #define TMR_IER(n) (0x0040 + ((n) << 2))
19 #define TMR_PLVR(n) (0x004c + ((n) << 2))
20 #define TMR_PLCR(n) (0x0058 + ((n) << 2))
21 #define TMR_WMER (0x0064)
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,msm8916.yaml | 54 reg = <0x00400000 0x62000>;
63 reg = <0x00500000 0x11000>;
72 reg = <0x00580000 0x14000>;
|
| D | interconnect.txt | 30 reg = <0x580000 0x14000>;
83 cpu@0 {
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/marvell/ |
| D | armada-37xx.txt | 34 reg = <0x14000 0x60>;
49 reg = <0x11500 0x40>;
|
| /kernel/linux/linux-6.6/arch/arm/mach-davinci/ |
| D | da8xx.h | 33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ufs/ |
| D | ti,j721e-ufs.yaml | 49 "^ufs@[0-9a-f]+$":
69 reg = <0x0 0x4e80000 0x0 0x100>;
75 ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
81 reg = <0x0 0x4000 0x0 0x10000>;
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/ufs/ |
| D | ti,j721e-ufs.yaml | 49 "^ufs@[0-9a-f]+$":
68 reg = <0x0 0x4e80000 0x0 0x100>;
74 ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
80 reg = <0x0 0x4000 0x0 0x10000>;
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interconnect/ |
| D | interconnect.txt | 30 reg = <0x580000 0x14000>;
83 cpu@0 {
|
| /kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/xlr/ |
| D | iomap.h | 38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
|
| /kernel/linux/linux-5.10/drivers/remoteproc/ |
| D | mtk_common.h | 15 #define MT8183_SW_RSTN 0x0
16 #define MT8183_SW_RSTN_BIT BIT(0)
17 #define MT8183_SCP_TO_HOST 0x1C
18 #define MT8183_SCP_IPC_INT_BIT BIT(0)
20 #define MT8183_HOST_TO_SCP 0x28
21 #define MT8183_HOST_IPC_INT_BIT BIT(0)
22 #define MT8183_WDT_CFG 0x84
23 #define MT8183_SCP_CLK_SW_SEL 0x4000
24 #define MT8183_SCP_CLK_DIV_SEL 0x4024
25 #define MT8183_SCP_SRAM_PDN 0x402C
[all …]
|
| /kernel/linux/linux-6.6/drivers/remoteproc/ |
| D | mtk_common.h | 15 #define MT8183_SW_RSTN 0x0
16 #define MT8183_SW_RSTN_BIT BIT(0)
17 #define MT8183_SCP_TO_HOST 0x1C
18 #define MT8183_SCP_IPC_INT_BIT BIT(0)
20 #define MT8183_HOST_TO_SCP 0x28
21 #define MT8183_HOST_IPC_INT_BIT BIT(0)
22 #define MT8183_WDT_CFG 0x84
23 #define MT8183_SCP_CLK_SW_SEL 0x4000
24 #define MT8183_SCP_CLK_DIV_SEL 0x4024
25 #define MT8183_SCP_SRAM_PDN 0x402C
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/intel/atom/sst/ |
| D | sst_acpi.c | 38 #define SST_BYT_IRAM_PHY_START 0xff2c0000
39 #define SST_BYT_IRAM_PHY_END 0xff2d4000
40 #define SST_BYT_DRAM_PHY_START 0xff300000
41 #define SST_BYT_DRAM_PHY_END 0xff320000
42 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
43 #define SST_BYT_IMR_VIRT_END 0xc01fffff
44 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
45 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
46 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
47 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/intel/atom/sst/ |
| D | sst_acpi.c | 38 #define SST_BYT_IRAM_PHY_START 0xff2c0000
39 #define SST_BYT_IRAM_PHY_END 0xff2d4000
40 #define SST_BYT_DRAM_PHY_START 0xff300000
41 #define SST_BYT_DRAM_PHY_END 0xff320000
42 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
43 #define SST_BYT_IMR_VIRT_END 0xc01fffff
44 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
45 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
46 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
47 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-bman1-portals.dtsi | 40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
|
| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-bman1-portals.dtsi | 40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
|
| /kernel/linux/linux-6.6/drivers/reset/ |
| D | reset-qcom-aoss.c | 30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
|
| /kernel/linux/linux-5.10/drivers/reset/ |
| D | reset-qcom-aoss.c | 30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
|