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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dti,c64x+megamod-pic.txt7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
23 core_pic: interrupt-controller@0 {
62 interrupts 0 - 3 (combined interrupt sources) are
78 reg = <0x1800000 0x1000>;
84 combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
92 reg = <0x1800000 0x1000>;
95 ti,c64x+megamod-pic-mux = < 0 0 0 0
96 32 0 0 0
97 0 0 0 0 >;
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath10k/
Dahb.h34 #define ATH10K_GCC_REG_BASE 0x1800000
35 #define ATH10K_GCC_REG_SIZE 0x60000
37 #define ATH10K_TCSR_REG_BASE 0x1900000
38 #define ATH10K_TCSR_REG_SIZE 0x80000
40 #define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020
41 #define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014
43 #define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030
45 #define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000
46 #define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004
49 #define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath10k/
Dahb.h34 #define ATH10K_GCC_REG_BASE 0x1800000
35 #define ATH10K_GCC_REG_SIZE 0x60000
37 #define ATH10K_TCSR_REG_BASE 0x1900000
38 #define ATH10K_TCSR_REG_SIZE 0x80000
40 #define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020
41 #define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014
43 #define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030
45 #define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000
46 #define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004
49 #define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dqcom,gcc-ipq4019.yaml46 reg = <0x1800000 0x60000>;
Dqcom,gcc-msm8976.yaml65 reg = <0x1800000 0x80000>;
70 <&dsi0_phy 0>,
72 <&dsi1_phy 0>;
/kernel/linux/linux-6.6/arch/arm/mach-versatile/
Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-integrator/
Dhardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
20 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
30 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
31 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
45 #define INTEGRATOR_SSRAM_BASE 0x00000000
46 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
49 #define INTEGRATOR_FLASH_BASE 0x24000000
52 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
58 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/kernel/linux/linux-5.10/arch/c6x/boot/dts/
Dtms320c6457.dtsi9 #size-cells = <0>;
11 cpu@0 {
14 reg = <0>;
36 reg = <0x1800000 0x1000>;
41 reg = <0x01840000 0x8400>;
46 reg = <0x02880800 0x400>;
48 ti,dscr-devstat = <0x20>;
49 ti,dscr-silicon-rev = <0x18 28 0xf>;
50 ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
51 0x118 0 0 1 2>;
[all …]
Dtms320c6474.dtsi9 #size-cells = <0>;
11 cpu@0 {
13 reg = <0>;
45 reg = <0x1800000 0x1000>;
51 reg = <0x01840000 0x8400>;
56 ti,core-mask = < 0x04 >;
57 reg = <0x2940000 0x40>;
62 ti,core-mask = < 0x02 >;
63 reg = <0x2950000 0x40>;
68 ti,core-mask = < 0x01 >;
[all …]
Dtms320c6455.dtsi9 #size-cells = <0>;
11 cpu@0 {
14 reg = <0>;
38 reg = <0x1800000 0x1000>;
44 reg = <0x01840000 0x8400>;
51 reg = <0x70000000 0x100>;
52 ranges = <0x2 0x0 0xa0000000 0x00000008
53 0x3 0x0 0xb0000000 0x00400000
54 0x4 0x0 0xc0000000 0x10000000
55 0x5 0x0 0xD0000000 0x10000000>;
[all …]
Dtms320c6472.dtsi9 #size-cells = <0>;
11 cpu@0 {
13 reg = <0>;
60 reg = <0x1800000 0x1000>;
66 reg = <0x01840000 0x8400>;
71 ti,core-mask = < 0x01 >;
72 reg = <0x25e0000 0x40>;
77 ti,core-mask = < 0x02 >;
78 reg = <0x25f0000 0x40>;
83 ti,core-mask = < 0x04 >;
[all …]
Dtms320c6678.dtsi9 #size-cells = <0>;
11 cpu@0 {
13 reg = <0>;
70 reg = <0x1800000 0x1000>;
76 reg = <0x01840000 0x8400>;
81 ti,core-mask = < 0x01 >;
82 reg = <0x2280000 0x40>;
87 ti,core-mask = < 0x02 >;
88 reg = <0x2290000 0x40>;
93 ti,core-mask = < 0x04 >;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmscc-ocelot.txt18 - "portX" with X from 0 to the number of last port index available on that
31 - #size-cells: Must be 0
46 reg = <0x1010000 0x10000>,
47 <0x1030000 0x10000>,
48 <0x1080000 0x100>,
49 <0x10e0000 0x10000>,
50 <0x11e0000 0x100>,
51 <0x11f0000 0x100>,
52 <0x1200000 0x100>,
53 <0x1210000 0x100>,
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dkirkwood-topkick.dts13 reg = <0x00000000 0x10000000>;
34 pinctrl-0 = <&pmx_sw_left &pmx_sw_right
103 pinctrl-0 = <&pmx_sdio>;
125 pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red
156 #size-cells = <0>;
157 pinctrl-0 = <&pmx_sata0_pwr_enable>;
169 gpio = <&gpio1 4 0>;
177 partition@0 {
179 reg = <0x0000000 0x180000>;
184 reg = <0x0180000 0x20000>;
[all …]
Dkirkwood-netgear_readynas_duo_v2.dts19 reg = <0x00000000 0x10000000>;
78 #clock-cells = <0>;
88 reg = <0x32>;
93 reg = <0x3e>;
95 fan_gear_mode = <0>;
97 pwm_polarity = <0>;
113 pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity
147 pinctrl-0 = <&pmx_button_power &pmx_button_backup
172 pinctrl-0 = <&pmx_poweroff>;
180 #size-cells = <0>;
[all …]
Dkirkwood-netgear_readynas_nv+_v2.dts19 reg = <0x00000000 0x10000000>;
83 #clock-cells = <0>;
93 reg = <0x32>;
98 reg = <0x3e>;
100 fan_gear_mode = <0>;
102 pwm_polarity = <0>;
132 pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup
171 pinctrl-0 = <&pmx_button_power &pmx_button_backup
196 pinctrl-0 = <&pmx_poweroff>;
204 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Dkirkwood-topkick.dts13 reg = <0x00000000 0x10000000>;
34 pinctrl-0 = <&pmx_sw_left &pmx_sw_right
103 pinctrl-0 = <&pmx_sdio>;
125 pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red
156 #size-cells = <0>;
157 pinctrl-0 = <&pmx_sata0_pwr_enable>;
169 gpio = <&gpio1 4 0>;
177 partition@0 {
179 reg = <0x0000000 0x180000>;
184 reg = <0x0180000 0x20000>;
[all …]
Dkirkwood-netgear_readynas_duo_v2.dts19 reg = <0x00000000 0x10000000>;
78 #clock-cells = <0>;
88 reg = <0x32>;
93 reg = <0x3e>;
95 fan_gear_mode = <0>;
97 pwm_polarity = <0>;
113 pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity
147 pinctrl-0 = <&pmx_button_power &pmx_button_backup
172 pinctrl-0 = <&pmx_poweroff>;
180 #size-cells = <0>;
[all …]
Dkirkwood-netgear_readynas_nv+_v2.dts19 reg = <0x00000000 0x10000000>;
83 #clock-cells = <0>;
93 reg = <0x32>;
98 reg = <0x3e>;
100 fan_gear_mode = <0>;
102 pwm_polarity = <0>;
132 pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup
171 pinctrl-0 = <&pmx_button_power &pmx_button_backup
196 pinctrl-0 = <&pmx_poweroff>;
204 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dmscc,vsc7514-switch.yaml38 "^port@[0-9a-f]+$":
55 "^port@[0-9a-f]+$":
142 reg = <0x1010000 0x10000>,
143 <0x1030000 0x10000>,
144 <0x1080000 0x100>,
145 <0x10e0000 0x10000>,
146 <0x11e0000 0x100>,
147 <0x11f0000 0x100>,
148 <0x1200000 0x100>,
149 <0x1210000 0x100>,
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/mscc/
Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/mscc/
Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Ddrxd_map_firm.h18 #define HI_COMM_EXEC__A 0x400000
19 #define HI_COMM_MB__A 0x400002
20 #define HI_CT_REG_COMM_STATE__A 0x410001
21 #define HI_RA_RAM_SRV_RES__A 0x420031
22 #define HI_RA_RAM_SRV_CMD__A 0x420032
23 #define HI_RA_RAM_SRV_CMD_RESET 0x2
24 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3
25 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
26 #define HI_RA_RAM_SRV_RST_KEY__A 0x420033
27 #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
[all …]
Ddrxk_map.h2 #define AUD_COMM_EXEC__A 0x1000000
3 #define AUD_COMM_EXEC_STOP 0x0
4 #define FEC_COMM_EXEC__A 0x1C00000
5 #define FEC_COMM_EXEC_STOP 0x0
6 #define FEC_COMM_EXEC_ACTIVE 0x1
7 #define FEC_DI_COMM_EXEC__A 0x1C20000
8 #define FEC_DI_COMM_EXEC_STOP 0x0
9 #define FEC_DI_INPUT_CTL__A 0x1C20016
10 #define FEC_RS_COMM_EXEC__A 0x1C30000
11 #define FEC_RS_COMM_EXEC_STOP 0x0
[all …]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Ddrxd_map_firm.h18 #define HI_COMM_EXEC__A 0x400000
19 #define HI_COMM_MB__A 0x400002
20 #define HI_CT_REG_COMM_STATE__A 0x410001
21 #define HI_RA_RAM_SRV_RES__A 0x420031
22 #define HI_RA_RAM_SRV_CMD__A 0x420032
23 #define HI_RA_RAM_SRV_CMD_RESET 0x2
24 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3
25 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
26 #define HI_RA_RAM_SRV_RST_KEY__A 0x420033
27 #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
[all …]

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