Searched +full:0 +full:x1ff00000 (Results 1 – 25 of 61) sorted by relevance
123
| /kernel/linux/linux-6.6/include/net/ |
| D | ieee80211_radiotap.h | 28 * @it_version: radiotap version, always 0
53 /* version is always 0 */
54 #define PKTHDR_RADIOTAP_VERSION 0
58 IEEE80211_RADIOTAP_TSFT = 0,
97 IEEE80211_RADIOTAP_F_CFP = 0x01,
98 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
99 IEEE80211_RADIOTAP_F_WEP = 0x04,
100 IEEE80211_RADIOTAP_F_FRAG = 0x08,
101 IEEE80211_RADIOTAP_F_FCS = 0x10,
102 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | cn9130.dtsi | 29 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
30 0xe0000000 + ((iface - 1) * 0x1000000))
31 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/ |
| D | cn9130.dtsi | 29 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
30 0xe0000000 + ((iface - 1) * 0x1000000))
31 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/partitions/ |
| D | u-boot.yaml | 43 partition@0 {
45 reg = <0x0 0x100000>;
53 reg = <0x100000 0x1ff00000>;
|
| /kernel/linux/linux-6.6/arch/sh/drivers/pci/ |
| D | pci-sh7780.c | 24 # define PCICR_ENDIANNESS 0
31 .start = 0x1000,
35 .name = "PCI MEM 0",
36 .start = 0xfd000000,
37 .end = 0xfd000000 + SZ_16M - 1,
41 .start = 0x10000000,
42 .end = 0x10000000 + SZ_64M - 1,
49 .start = 0xc0000000,
50 .end = 0xc0000000 + SZ_512M - 1,
59 .io_offset = 0,
[all …]
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| /kernel/linux/linux-5.10/arch/sh/drivers/pci/ |
| D | pci-sh7780.c | 24 # define PCICR_ENDIANNESS 0
31 .start = 0x1000,
35 .name = "PCI MEM 0",
36 .start = 0xfd000000,
37 .end = 0xfd000000 + SZ_16M - 1,
41 .start = 0x10000000,
42 .end = 0x10000000 + SZ_64M - 1,
49 .start = 0xc0000000,
50 .end = 0xc0000000 + SZ_512M - 1,
59 .io_offset = 0,
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/ |
| D | ar9002_phy.h | 19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
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| D | ar9003_phy.h | 23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/ |
| D | ar9002_phy.h | 19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
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| D | ar9003_phy.h | 23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
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| /kernel/linux/linux-6.6/arch/mips/sni/ |
| D | a20r.c | 30 PORT(0x3f8, 4),
31 PORT(0x2f8, 3),
45 .start = 0x1c081ffc,
46 .end = 0x1c081fff,
59 .start = 0x18000000,
60 .end = 0x18000004,
64 .start = 0x18010000,
65 .end = 0x18010004,
69 .start = 0x1ff00000,
70 .end = 0x1ff00020,
[all …]
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| /kernel/linux/linux-5.10/arch/mips/sni/ |
| D | a20r.c | 30 PORT(0x3f8, 4),
31 PORT(0x2f8, 3),
45 .start = 0x1c081ffc,
46 .end = 0x1c081fff,
59 .start = 0x18000000,
60 .end = 0x18000004,
64 .start = 0x18010000,
65 .end = 0x18010004,
69 .start = 0x1ff00000,
70 .end = 0x1ff00020,
[all …]
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| /kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
| D | dcore0_hmmu0_mmu_masks.h | 24 #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0
25 #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1
28 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0
29 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1
31 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2
34 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0
35 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1
37 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2
39 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4
41 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8
[all …]
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| /kernel/linux/linux-6.6/arch/mips/include/asm/ |
| D | sni.h | 30 #define SNI_CPU_M8021 0x01
31 #define SNI_CPU_M8030 0x04
32 #define SNI_CPU_M8031 0x06
33 #define SNI_CPU_M8034 0x0f
34 #define SNI_CPU_M8037 0x07
35 #define SNI_CPU_M8040 0x05
36 #define SNI_CPU_M8043 0x09
37 #define SNI_CPU_M8050 0x0b
38 #define SNI_CPU_M8053 0x0d
40 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | sni.h | 30 #define SNI_CPU_M8021 0x01
31 #define SNI_CPU_M8030 0x04
32 #define SNI_CPU_M8031 0x06
33 #define SNI_CPU_M8034 0x0f
34 #define SNI_CPU_M8037 0x07
35 #define SNI_CPU_M8040 0x05
36 #define SNI_CPU_M8043 0x09
37 #define SNI_CPU_M8050 0x0b
38 #define SNI_CPU_M8053 0x0d
40 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | msm8992-bullhead-rev-101.dts | 15 qcom,msm-id = <251 0>, <252 0>;
16 qcom,board-id = <0xb64 0>;
17 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
37 reg = <0x0 0x1ff00000 0x0 0x40000>;
38 console-size = <0x10000>;
39 record-size = <0x10000>;
40 ftrace-size = <0x10000>;
41 pmsg-size = <0x20000>;
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| /kernel/linux/linux-6.6/arch/mips/include/asm/mach-loongson64/ |
| D | loongson.h | 62 for (x = 0; x < 100000; x++) \
75 #define LOONGSON_FLASH_BASE 0x1c000000
76 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
79 #define LOONGSON_LIO0_BASE 0x1e000000
80 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
83 #define LOONGSON_BOOT_BASE 0x1fc00000
84 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
86 #define LOONGSON_REG_BASE 0x1fe00000
87 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
90 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-loongson64/ |
| D | loongson.h | 37 for (x = 0; x < 100000; x++) \
50 #define LOONGSON_FLASH_BASE 0x1c000000
51 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
54 #define LOONGSON_LIO0_BASE 0x1e000000
55 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
58 #define LOONGSON_BOOT_BASE 0x1fc00000
59 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
61 #define LOONGSON_REG_BASE 0x1fe00000
62 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
65 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/ |
| D | msm8992-lg-bullhead.dtsi | 26 qcom,msm-id = <251 0>, <252 0>;
27 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
47 reg = <0x0 0x1ff00000 0x0 0x40000>;
48 console-size = <0x10000>;
49 record-size = <0x10000>;
50 ftrace-size = <0x10000>;
51 pmsg-size = <0x20000>;
55 reg = <0 0x03400000 0 0xc00000>;
60 reg = <0x0 0x05000000 0x0 0x1a00000>;
71 pm8994_regulators: regulators-0 {
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| /kernel/linux/linux-6.6/arch/mips/include/asm/mach-loongson2ef/ |
| D | loongson.h | 51 for (x = 0; x < 100000; x++) \
60 #define LOONGSON_FLASH_BASE 0x1c000000
61 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
64 #define LOONGSON_LIO0_BASE 0x1e000000
65 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
68 #define LOONGSON_BOOT_BASE 0x1fc00000
69 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
71 #define LOONGSON_REG_BASE 0x1fe00000
72 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
75 #define LOONGSON_LIO1_BASE 0x1ff00000
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-loongson2ef/ |
| D | loongson.h | 51 for (x = 0; x < 100000; x++) \
69 #define LOONGSON_FLASH_BASE 0x1c000000
70 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
73 #define LOONGSON_LIO0_BASE 0x1e000000
74 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
77 #define LOONGSON_BOOT_BASE 0x1fc00000
78 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
80 #define LOONGSON_REG_BASE 0x1fe00000
81 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
84 #define LOONGSON_LIO1_BASE 0x1ff00000
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mips-boards/ |
| D | bonito64.h | 42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
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| /kernel/linux/linux-6.6/arch/mips/include/asm/mips-boards/ |
| D | bonito64.h | 42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
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| /kernel/linux/linux-5.10/drivers/thermal/intel/ |
| D | intel_pch_thermal.c | 20 #define PCH_THERMAL_DID_HSW_1 0x9C24 /* Haswell PCH */
21 #define PCH_THERMAL_DID_HSW_2 0x8C24 /* Haswell PCH */
22 #define PCH_THERMAL_DID_WPT 0x9CA4 /* Wildcat Point */
23 #define PCH_THERMAL_DID_SKL 0x9D31 /* Skylake PCH */
24 #define PCH_THERMAL_DID_SKL_H 0xA131 /* Skylake PCH 100 series */
25 #define PCH_THERMAL_DID_CNL 0x9Df9 /* CNL PCH */
26 #define PCH_THERMAL_DID_CNL_H 0xA379 /* CNL-H PCH */
27 #define PCH_THERMAL_DID_CNL_LP 0x02F9 /* CNL-LP PCH */
28 #define PCH_THERMAL_DID_CML_H 0X06F9 /* CML-H PCH */
31 #define WPT_TEMP 0x0000 /* Temperature */
[all …]
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| /kernel/linux/linux-6.6/drivers/thermal/intel/ |
| D | intel_pch_thermal.c | 22 #define PCH_THERMAL_DID_HSW_1 0x9C24 /* Haswell PCH */
23 #define PCH_THERMAL_DID_HSW_2 0x8C24 /* Haswell PCH */
24 #define PCH_THERMAL_DID_WPT 0x9CA4 /* Wildcat Point */
25 #define PCH_THERMAL_DID_SKL 0x9D31 /* Skylake PCH */
26 #define PCH_THERMAL_DID_SKL_H 0xA131 /* Skylake PCH 100 series */
27 #define PCH_THERMAL_DID_CNL 0x9Df9 /* CNL PCH */
28 #define PCH_THERMAL_DID_CNL_H 0xA379 /* CNL-H PCH */
29 #define PCH_THERMAL_DID_CNL_LP 0x02F9 /* CNL-LP PCH */
30 #define PCH_THERMAL_DID_CML_H 0X06F9 /* CML-H PCH */
31 #define PCH_THERMAL_DID_LWB 0xA1B1 /* Lewisburg PCH */
[all …]
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