| /kernel/linux/linux-5.10/arch/arm/mach-mv78xx0/ |
| D | mv78xx0.h | 20 * f0800000 PCIe #0 I/O space
32 * fee00000 f0800000 64K PCIe #0 I/O space
42 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
48 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
51 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-mv78xx0/ |
| D | mv78xx0.h | 17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
|
| /kernel/linux/linux-6.6/drivers/hwmon/ |
| D | jc42.c | 27 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
30 #define JC42_REG_CAP 0x00
31 #define JC42_REG_CONFIG 0x01
32 #define JC42_REG_TEMP_UPPER 0x02
33 #define JC42_REG_TEMP_LOWER 0x03
34 #define JC42_REG_TEMP_CRITICAL 0x04
35 #define JC42_REG_TEMP 0x05
36 #define JC42_REG_MANID 0x06
37 #define JC42_REG_DEVICEID 0x07
38 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
[all …]
|
| /kernel/linux/linux-5.10/drivers/hwmon/ |
| D | jc42.c | 26 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
29 #define JC42_REG_CAP 0x00
30 #define JC42_REG_CONFIG 0x01
31 #define JC42_REG_TEMP_UPPER 0x02
32 #define JC42_REG_TEMP_LOWER 0x03
33 #define JC42_REG_TEMP_CRITICAL 0x04
34 #define JC42_REG_TEMP 0x05
35 #define JC42_REG_MANID 0x06
36 #define JC42_REG_DEVICEID 0x07
37 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| D | rt715-sdca-sdw.c | 25 case 0x201a ... 0x2027: in rt715_sdca_readable_register()
26 case 0x2029 ... 0x202a: in rt715_sdca_readable_register()
27 case 0x202d ... 0x2034: in rt715_sdca_readable_register()
28 case 0x2200 ... 0x2204: in rt715_sdca_readable_register()
29 case 0x2206 ... 0x2212: in rt715_sdca_readable_register()
30 case 0x2230 ... 0x2239: in rt715_sdca_readable_register()
31 case 0x2f5b: in rt715_sdca_readable_register()
43 case 0x201b: in rt715_sdca_volatile_register()
44 case 0x201c: in rt715_sdca_volatile_register()
45 case 0x201d: in rt715_sdca_volatile_register()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/reg_srcs/ |
| D | r100 | 1 r100 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
|
| D | r200 | 1 r200 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/reg_srcs/ |
| D | r100 | 1 r100 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
|
| D | r200 | 1 r200 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
|
| /kernel/linux/linux-5.10/drivers/scsi/ufs/ |
| D | ufs-mediatek.h | 15 #define REG_UFS_REFCLK_CTRL 0x144
16 #define REG_UFS_EXTREG 0x2100
17 #define REG_UFS_MPHYCTRL 0x2200
18 #define REG_UFS_REJECT_MON 0x22AC
19 #define REG_UFS_DEBUG_SEL 0x22C0
20 #define REG_UFS_PROBE 0x22C8
27 #define REFCLK_RELEASE 0x0
28 #define REFCLK_REQUEST BIT(0)
52 #define VS_DEBUGCLOCKENABLE 0xD0A1
53 #define VS_SAVEPOWERCONTROL 0xD0A6
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | qcom,sm8250-camss.yaml | 113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-pcie.dtsi | 8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-pcie.dtsi | 8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/ |
| D | dp_panel.h | 17 #define DPRX_EXTENDED_DPCD_FIELD 0x2200
|
| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | cpu.h | 16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
|
| /kernel/linux/linux-6.6/arch/mips/include/asm/ |
| D | cpu.h | 16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/ |
| D | dp_panel.h | 16 #define DPRX_EXTENDED_DPCD_FIELD 0x2200
|
| /kernel/linux/linux-5.10/drivers/net/wireless/rsi/ |
| D | rsi_sdio.h | 32 BUFFER_FULL = 0x0,
33 BUFFER_AVAILABLE = 0x2,
34 FIRMWARE_ASSERT_IND = 0x3,
35 MSDU_PACKET_PENDING = 0x4,
36 UNKNOWN_INT = 0XE
40 #define PKT_BUFF_SEMI_FULL 0
51 #define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3
52 #define RSI_FN1_INT_REGISTER 0xf9
53 #define RSI_INT_ENABLE_REGISTER 0x04
54 #define RSI_INT_ENABLE_MASK 0xfc
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/wireless/rsi/ |
| D | rsi_sdio.h | 32 BUFFER_FULL = 0x0,
33 BUFFER_AVAILABLE = 0x2,
34 FIRMWARE_ASSERT_IND = 0x3,
35 MSDU_PACKET_PENDING = 0x4,
36 UNKNOWN_INT = 0XE
40 #define PKT_BUFF_SEMI_FULL 0
51 #define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3
52 #define RSI_FN1_INT_REGISTER 0xf9
53 #define RSI_INT_ENABLE_REGISTER 0x04
54 #define RSI_INT_ENABLE_MASK 0xfc
[all …]
|
| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/ |
| D | t1024si-post.dtsi | 48 ranges = <0x0 0xf 0xfe140000 0x40000>;
49 reg = <0xf 0xfe140000 0 0x480>;
52 brg-frequency = <0>;
53 bus-frequency = <0>;
60 reg = <0x180000 1000>;
61 interrupts = <74 2 0 0>;
69 #address-cells = <0>;
71 reg = <0x80 0x80>;
72 interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
77 reg = <0x2000 0x200>;
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | t1024si-post.dtsi | 48 ranges = <0x0 0xf 0xfe140000 0x40000>;
49 reg = <0xf 0xfe140000 0 0x480>;
52 brg-frequency = <0>;
53 bus-frequency = <0>;
60 reg = <0x180000 1000>;
61 interrupts = <74 2 0 0>;
69 #address-cells = <0>;
71 reg = <0x80 0x80>;
72 interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
77 reg = <0x2000 0x200>;
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | qcom,msm8996-qmp-pcie-phy.yaml | 57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x130>,
150 <0x1200 0x200>,
151 <0x1400 0x1dc>;
156 #clock-cells = <0>;
159 #phy-cells = <0>;
[all …]
|
| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/ |
| D | a4m072.dts | 27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | a4m072.dts | 27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/pci/ |
| D | g84.c | 39 return (nvkm_rd32(device, 0x00154c) & 0x1) + 1; in g84_pcie_version()
46 nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0)); in g84_pcie_set_version()
53 nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0); in g84_pcie_set_cap_speed()
59 u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000; in g84_pcie_cur_speed()
61 case 0x30000: in g84_pcie_cur_speed()
63 case 0x20000: in g84_pcie_cur_speed()
65 case 0x10000: in g84_pcie_cur_speed()
74 u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300; in g84_pcie_max_speed()
75 if (reg_v == 0x2200) in g84_pcie_max_speed()
86 mask_value = 0x20; in g84_pcie_set_link_speed()
[all …]
|