| /kernel/linux/linux-5.10/drivers/mfd/ |
| D | si476x-prop.c | 25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array() 38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range() 49 0x0000, in si476x_core_is_valid_property_a10() 50 0x0500, 0x0501, in si476x_core_is_valid_property_a10() 51 0x0600, in si476x_core_is_valid_property_a10() 52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10() 53 0x0718, in si476x_core_is_valid_property_a10() 54 0x1207, 0x1208, in si476x_core_is_valid_property_a10() 55 0x2007, in si476x_core_is_valid_property_a10() 56 0x2300, in si476x_core_is_valid_property_a10() [all …]
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| /kernel/linux/linux-6.6/drivers/mfd/ |
| D | si476x-prop.c | 25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array() 38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range() 49 0x0000, in si476x_core_is_valid_property_a10() 50 0x0500, 0x0501, in si476x_core_is_valid_property_a10() 51 0x0600, in si476x_core_is_valid_property_a10() 52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10() 53 0x0718, in si476x_core_is_valid_property_a10() 54 0x1207, 0x1208, in si476x_core_is_valid_property_a10() 55 0x2007, in si476x_core_is_valid_property_a10() 56 0x2300, in si476x_core_is_valid_property_a10() [all …]
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| /kernel/linux/linux-5.10/drivers/staging/gdm724x/ |
| D | hci.h | 7 #define LTE_GET_INFORMATION 0x3002 8 #define LTE_GET_INFORMATION_RESULT 0xB003 9 #define MAC_ADDRESS 0xA2 11 #define LTE_LINK_ON_OFF_INDICATION 0xB133 12 #define LTE_PDN_TABLE_IND 0xB143 14 #define LTE_TX_SDU 0x3200 15 #define LTE_RX_SDU 0xB201 16 #define LTE_TX_MULTI_SDU 0x3202 17 #define LTE_RX_MULTI_SDU 0xB203 19 #define LTE_DL_SDU_FLOW_CONTROL 0x3305 [all …]
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| /kernel/linux/linux-6.6/drivers/staging/gdm724x/ |
| D | hci.h | 7 #define LTE_GET_INFORMATION 0x3002 8 #define LTE_GET_INFORMATION_RESULT 0xB003 9 #define MAC_ADDRESS 0xA2 11 #define LTE_LINK_ON_OFF_INDICATION 0xB133 12 #define LTE_PDN_TABLE_IND 0xB143 14 #define LTE_TX_SDU 0x3200 15 #define LTE_RX_SDU 0xB201 16 #define LTE_TX_MULTI_SDU 0x3202 17 #define LTE_RX_MULTI_SDU 0xB203 19 #define LTE_DL_SDU_FLOW_CONTROL 0x3305 [all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbevf/ |
| D | regs.h | 7 #define IXGBE_VFCTRL 0x00000 8 #define IXGBE_VFSTATUS 0x00008 9 #define IXGBE_VFLINKS 0x00010 10 #define IXGBE_VFFRTIMER 0x00048 11 #define IXGBE_VFRXMEMWRAP 0x03190 12 #define IXGBE_VTEICR 0x00100 13 #define IXGBE_VTEICS 0x00104 14 #define IXGBE_VTEIMS 0x00108 15 #define IXGBE_VTEIMC 0x0010C 16 #define IXGBE_VTEIAC 0x00110 [all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/ixgbevf/ |
| D | regs.h | 7 #define IXGBE_VFCTRL 0x00000 8 #define IXGBE_VFSTATUS 0x00008 9 #define IXGBE_VFLINKS 0x00010 10 #define IXGBE_VFFRTIMER 0x00048 11 #define IXGBE_VFRXMEMWRAP 0x03190 12 #define IXGBE_VTEICR 0x00100 13 #define IXGBE_VTEICS 0x00104 14 #define IXGBE_VTEIMS 0x00108 15 #define IXGBE_VTEIMC 0x0010C 16 #define IXGBE_VTEIAC 0x00110 [all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/mediatek/ |
| D | mtk_dp_reg.h | 9 #define SEC_OFFSET 0x4000 15 /* offset: 0x0 */ 16 #define DP_PHY_GLB_BIAS_GEN_00 0x0 18 #define DP_PHY_GLB_DPAUX_TX 0x8 20 #define MTK_DP_0034 0x34 36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0) 37 #define DP_PHY_LANE_TX_0 0x104 40 #define DP_PHY_LANE_TX_1 0x204 43 #define DP_PHY_LANE_TX_2 0x304 46 #define DP_PHY_LANE_TX_3 0x404 [all …]
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| /kernel/linux/linux-6.6/drivers/media/rc/keymaps/ |
| D | rc-dreambox.c | 22 { 0x3200, KEY_POWER }, 25 { 0x3290, KEY_HELP }, 28 { 0x3201, KEY_1 }, 29 { 0x3202, KEY_2 }, 30 { 0x3203, KEY_3 }, 31 { 0x3204, KEY_4 }, 32 { 0x3205, KEY_5 }, 33 { 0x3206, KEY_6 }, 34 { 0x3207, KEY_7 }, 35 { 0x3208, KEY_8 }, [all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | qcom,msm8996-qmp-pcie-phy.yaml | 57 "^phy@[0-9a-f]+$": 92 const: 0 98 const: 0 130 reg = <0x34000 0x488>; 133 ranges = <0x0 0x34000 0x4000>; 149 reg = <0x1000 0x130>, 150 <0x1200 0x200>, 151 <0x1400 0x1dc>; 156 #clock-cells = <0>; 159 #phy-cells = <0>; [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | polaris10_smumgr.c | 55 #define POLARIS10_SMC_SIZE 0x20000 58 #define MC_CG_ARB_FREQ_F1 0x0b 63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, 65 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5… 83 …0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000… 84 …0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000… 85 …0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000… 86 …0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000… 87 …0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100… [all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | polaris10_smumgr.c | 55 #define POLARIS10_SMC_SIZE 0x20000 58 #define MC_CG_ARB_FREQ_F1 0x0b 63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, 65 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5… 83 …0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000… 84 …0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000… 85 …0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000… 86 …0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000… 87 …0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100… [all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | mpc8569si-post.dtsi | 39 interrupts = <19 2 0 0>; 40 sleep = <&pmc 0x08000000>; 43 /* controller at 0xa000 */ 49 bus-range = <0 255>; 51 interrupts = <26 2 0 0>; 52 sleep = <&pmc 0x20000000>; 54 pcie@0 { 55 reg = <0 0 0 0 0>; 60 interrupts = <26 2 0 0>; 61 interrupt-map-mask = <0xf800 0 0 7>; [all …]
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| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/ |
| D | mpc8569si-post.dtsi | 39 interrupts = <19 2 0 0>; 40 sleep = <&pmc 0x08000000>; 43 /* controller at 0xa000 */ 49 bus-range = <0 255>; 51 interrupts = <26 2 0 0>; 52 sleep = <&pmc 0x20000000>; 54 pcie@0 { 55 reg = <0 0 0 0 0>; 60 interrupts = <26 2 0 0>; 61 interrupt-map-mask = <0xf800 0 0 7>; [all …]
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| /kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/ |
| D | global1.h | 16 /* Offset 0x00: Switch Global Status Register */ 17 #define MV88E6XXX_G1_STS 0x00 18 #define MV88E6352_G1_STS_PPU_STATE 0x8000 19 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000 20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000 21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000 22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000 23 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000 24 #define MV88E6XXX_G1_STS_INIT_READY 0x0800 34 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0 [all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb/ |
| D | espi.c | 47 #define TRICN_CMD_READ 0x11 48 #define TRICN_CMD_WRITE 0x21 62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write() 86 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init() 87 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init() 88 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init() 91 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init() 93 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init() 95 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init() 96 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init() [all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/ |
| D | espi.c | 56 #define TRICN_CMD_READ 0x11 57 #define TRICN_CMD_WRITE 0x21 71 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write() 95 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init() 96 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init() 97 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init() 100 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init() 102 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init() 104 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init() 105 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init() [all …]
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| /kernel/linux/linux-5.10/drivers/ata/ |
| D | sata_vsc.c | 36 VSC_MMIO_BAR = 0, 39 VSC_SATA_INT_STAT_OFFSET = 0x00, 40 VSC_SATA_INT_MASK_OFFSET = 0x04, 43 VSC_SATA_TF_CMD_OFFSET = 0x00, 44 VSC_SATA_TF_DATA_OFFSET = 0x00, 45 VSC_SATA_TF_ERROR_OFFSET = 0x04, 46 VSC_SATA_TF_FEATURE_OFFSET = 0x06, 47 VSC_SATA_TF_NSECT_OFFSET = 0x08, 48 VSC_SATA_TF_LBAL_OFFSET = 0x0c, 49 VSC_SATA_TF_LBAM_OFFSET = 0x10, [all …]
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| /kernel/linux/linux-6.6/drivers/ata/ |
| D | sata_vsc.c | 36 VSC_MMIO_BAR = 0, 39 VSC_SATA_INT_STAT_OFFSET = 0x00, 40 VSC_SATA_INT_MASK_OFFSET = 0x04, 43 VSC_SATA_TF_CMD_OFFSET = 0x00, 44 VSC_SATA_TF_DATA_OFFSET = 0x00, 45 VSC_SATA_TF_ERROR_OFFSET = 0x04, 46 VSC_SATA_TF_FEATURE_OFFSET = 0x06, 47 VSC_SATA_TF_NSECT_OFFSET = 0x08, 48 VSC_SATA_TF_LBAL_OFFSET = 0x0c, 49 VSC_SATA_TF_LBAM_OFFSET = 0x10, [all …]
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| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/ |
| D | mpc836x_rdk.dts | 32 #size-cells = <0>; 34 PowerPC,8360@0 { 36 reg = <0>; 42 timebase-frequency = <0>; 43 bus-frequency = <0>; 44 clock-frequency = <0>; 51 reg = <0 0>; 60 ranges = <0 0xe0000000 0x200000>; 61 reg = <0xe0000000 0x200>; 63 bus-frequency = <0>; [all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | mpc836x_rdk.dts | 32 #size-cells = <0>; 34 PowerPC,8360@0 { 36 reg = <0>; 42 timebase-frequency = <0>; 43 bus-frequency = <0>; 44 clock-frequency = <0>; 51 reg = <0 0>; 60 ranges = <0 0xe0000000 0x200000>; 61 reg = <0xe0000000 0x200>; 63 bus-frequency = <0>; [all …]
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| D | mpc832x_mds.dts | 39 #size-cells = <0>; 41 PowerPC,8323@0 { 43 reg = <0x0>; 48 timebase-frequency = <0>; 49 bus-frequency = <0>; 50 clock-frequency = <0>; 56 reg = <0x00000000 0x08000000>; 61 reg = <0xf8000000 0x8000>; 69 ranges = <0x0 0xe0000000 0x00100000>; 70 reg = <0xe0000000 0x00000200>; [all …]
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| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| D | rt711-sdca-sdw.c | 22 case 0x201a ... 0x2027: in rt711_sdca_readable_register() 23 case 0x2029 ... 0x202a: in rt711_sdca_readable_register() 24 case 0x202d ... 0x2034: in rt711_sdca_readable_register() 25 case 0x2200 ... 0x2204: in rt711_sdca_readable_register() 26 case 0x2206 ... 0x2212: in rt711_sdca_readable_register() 27 case 0x2220 ... 0x2223: in rt711_sdca_readable_register() 28 case 0x2230 ... 0x2239: in rt711_sdca_readable_register() 29 case 0x2f01 ... 0x2f0f: in rt711_sdca_readable_register() 30 case 0x2f30 ... 0x2f36: in rt711_sdca_readable_register() 31 case 0x2f50 ... 0x2f5a: in rt711_sdca_readable_register() [all …]
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| /kernel/linux/linux-6.6/arch/powerpc/kernel/ |
| D | head_85xx.S | 71 li r25,0 /* phys kernel start (low) */ 72 li r24,0 /* CPU number */ 73 li r23,0 /* phys kernel start (high) */ 84 0: mflr r8 85 addis r3,r8,(is_second_reloc - 0b)@ha 86 lwz r19,(is_second_reloc - 0b)@l(r3) 103 addis r4,r8,(kernstart_addr - 0b)@ha 104 addi r4,r4,(kernstart_addr - 0b)@l 107 addis r6,r8,(memstart_addr - 0b)@ha 108 addi r6,r6,(memstart_addr - 0b)@l [all …]
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | head_fsl_booke.S | 70 li r25,0 /* phys kernel start (low) */ 71 li r24,0 /* CPU number */ 72 li r23,0 /* phys kernel start (high) */ 82 bl 0f 83 0: mflr r8 84 addis r3,r8,(is_second_reloc - 0b)@ha 85 lwz r19,(is_second_reloc - 0b)@l(r3) 102 addis r4,r8,(kernstart_addr - 0b)@ha 103 addi r4,r4,(kernstart_addr - 0b)@l 106 addis r6,r8,(memstart_addr - 0b)@ha [all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/amd/ |
| D | ariadne.h | 17 * Publication #16907, Rev. B, Amendment/0, May 1994 62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */ 63 #define CSR1 0x0100 /* - IADR[15:0] */ 64 #define CSR2 0x0200 /* - IADR[23:16] */ 65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */ 66 #define CSR4 0x0400 /* - Test and Features Control */ 67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */ 68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */ 69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */ 70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */ [all …]
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