Searched +full:0 +full:x3b4 (Results 1 – 25 of 119) sorted by relevance
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13 #define DISP_INTF_SEL 0x00414 #define INTR_EN 0x01015 #define INTR_STATUS 0x01416 #define INTR_CLEAR 0x01817 #define INTR2_EN 0x00818 #define INTR2_STATUS 0x00c19 #define INTR2_CLEAR 0x02c20 #define HIST_INTR_EN 0x01c21 #define HIST_INTR_STATUS 0x02022 #define HIST_INTR_CLEAR 0x024[all …]
13 #define DISP_INTF_SEL 0x00414 #define INTR_EN 0x01015 #define INTR_STATUS 0x01416 #define INTR_CLEAR 0x01817 #define INTR2_EN 0x00818 #define INTR2_STATUS 0x00c19 #define SSPP_SPARE 0x02820 #define INTR2_CLEAR 0x02c21 #define HIST_INTR_EN 0x01c22 #define HIST_INTR_STATUS 0x020[all …]
71 reg = <0x400e8000 0x4000>;74 <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,75 <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…[all …]
15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…[all …]
14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x015 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x316 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x017 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x318 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x019 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x020 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x021 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x022 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x023 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0[all …]
10 #define IMX_PAD_SION 0x4000000017 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x018 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x019 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x020 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x021 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x022 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x023 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x024 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x026 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0[all …]
16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x00017 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x00019 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x00020 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x00021 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x00023 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x00024 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x00025 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x00026 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x00028 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000[all …]
13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x014 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x015 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x016 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x017 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x018 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x019 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x020 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x021 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x022 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0[all …]
10 #define IMX_PAD_SION 0x4000000017 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x018 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x019 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x120 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x021 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x022 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x024 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x025 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x026 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1[all …]
15 #define HDMI_CORE_SYS_VND_IDL 0x016 #define HDMI_CORE_SYS_DEV_IDL 0x817 #define HDMI_CORE_SYS_DEV_IDH 0xC18 #define HDMI_CORE_SYS_DEV_REV 0x1019 #define HDMI_CORE_SYS_SRST 0x1420 #define HDMI_CORE_SYS_SYS_CTRL1 0x2021 #define HDMI_CORE_SYS_SYS_STAT 0x2422 #define HDMI_CORE_SYS_SYS_CTRL3 0x2823 #define HDMI_CORE_SYS_DCTL 0x3424 #define HDMI_CORE_SYS_DE_DLY 0xC8[all …]
15 #define RTK_PCI_CTRL 0x30018 #define REG_DBI_WDATA_V1 0x03E819 #define REG_DBI_RDATA_V1 0x03EC20 #define REG_DBI_FLAG_V1 0x03F026 #define REG_MDIO_V1 0x03F427 #define REG_PCIE_MIX_CFG 0x03F828 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)31 #define RTW_PCI_MDIO_PG_OFFS_G1 035 #define RTK_PCIE_LINK_CFG 0x071938 #define RTK_PCIE_CLKDLY_CTRL 0x0725[all …]
33 #define FENCE 0x02000 34 #define PGTBL_CTL 0x02020 35 #define PGTBL_ER 0x02024 36 #define LRING 0x0203037 #define IRING 0x0204038 #define HWS_PGA 0x02080 39 #define IPEIR 0x0208840 #define IPEHR 0x0208C 41 #define INSTDONE 0x02090 42 #define NOPID 0x02094[all …]
17 #define RTK_PCI_CTRL 0x30020 #define REG_DBI_WDATA_V1 0x03E821 #define REG_DBI_RDATA_V1 0x03EC22 #define REG_DBI_FLAG_V1 0x03F028 #define REG_MDIO_V1 0x03F429 #define REG_PCIE_MIX_CFG 0x03F830 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)33 #define RTW_PCI_MDIO_PG_OFFS_G1 037 #define RTK_PCIE_LINK_CFG 0x071940 #define BIT_CLKREQ_N_PAD BIT(0)[all …]
11 #define REG_VERSION 0x00012 #define REG_STATUS 0x10013 #define REG_STATUS2 0x10414 #define REG_ENGINES_AVAIL 0x10815 #define REG_FIFO_SIZES 0x10c16 #define REG_SEG_SIZE 0x11017 #define REG_GOPROC 0x12018 #define REG_ENCR_SEG_CFG 0x20019 #define REG_ENCR_SEG_SIZE 0x20420 #define REG_ENCR_SEG_START 0x208[all …]