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/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv04.c50 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); in nv04_instobj_wr32()
58 return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); in nv04_instobj_rd32()
77 return device->pri + 0x700000 + iobj->node->offset; in nv04_instobj_acquire()
136 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); in nv04_instobj_new()
148 return nvkm_rd32(imem->subdev.device, 0x700000 + addr); in nv04_instmem_rd32()
154 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); in nv04_instmem_wr32()
167 ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); in nv04_instmem_oneinit()
171 /* 0x00000-0x10000: reserve for probable vbios image */ in nv04_instmem_oneinit()
172 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, in nv04_instmem_oneinit()
177 /* 0x10000-0x18000: reserve for RAMHT */ in nv04_instmem_oneinit()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv04.c50 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); in nv04_instobj_wr32()
58 return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); in nv04_instobj_rd32()
77 return device->pri + 0x700000 + iobj->node->offset; in nv04_instobj_acquire()
136 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, in nv04_instobj_new()
149 return nvkm_rd32(imem->subdev.device, 0x700000 + addr); in nv04_instmem_rd32()
155 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); in nv04_instmem_wr32()
168 ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); in nv04_instmem_oneinit()
172 /* 0x00000-0x10000: reserve for probable vbios image */ in nv04_instmem_oneinit()
173 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, in nv04_instmem_oneinit()
178 /* 0x10000-0x18000: reserve for RAMHT */ in nv04_instmem_oneinit()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dmsm8994-huawei-angler-rev-101.dts17 qcom,msm-id = <207 0x20000>;
18 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
19 qcom,board-id = <8026 0>;
35 reg = <0 0x03401000 0 0x1000000>;
40 reg = <0 0x04800000 0 0x1900000>;
45 reg = <0 0x06300000 0 0x700000>;
54 pinctrl-0 = <&blsp1_uart2_default>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/misc/
Dti,j721e-esm.yaml50 reg = <0x0 0x700000 0x0 0x1000>;
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-davinci/
Dda8xx.h33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Dac5-98dx35xx-rd.dts30 memory@0 {
32 reg = <0x2 0x00000000 0x0 0x40000000>;
37 #phy-cells = <0>;
42 phy0: ethernet-phy@0 {
43 reg = <0>;
76 spiflash0: flash@0 {
81 reg = <0>;
86 partition@0 {
88 reg = <0x0 0x800000>;
93 reg = <0x800000 0x700000>;
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/netlogic/
Dxlp_rvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
[all …]
Dxlp_gvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/
Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa0000000 0x00 0x100000>;
37 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 reg = <0x00 0xa1000000 0x00 0x100000>;
49 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 reg = <0x00 0xa2000000 0x00 0x100000>;
61 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/ls/
Dls1021a-tqmls1021a.dtsi33 /* MC34VR500 DC/DC regulator at 0x8, managed by PMIC */
34 /* On-board PMC at 0x11 */
38 reg = <0x4c>;
44 reg = <0x51>;
50 reg = <0x54>;
59 reg = <0x8>;
67 qflash0: flash@0 {
74 reg = <0>;
81 uboot@0 {
83 reg = <0x0 0xe0000>;
[all …]
/kernel/linux/linux-6.6/arch/m68k/coldfire/
Dstmark2.c25 .size = 0x100000,
26 .offset = 0x0
29 .size = 0x700000,
49 .bus_num = 0,
56 /* SPI controller data, SPI (0) */
59 .bus_num = 0,
65 [0] = {
67 .end = MCFDSPI_BASE0 + 0xFF,
87 .id = 0,
107 __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL); in init_stmark2()
[all …]
/kernel/linux/linux-5.10/arch/m68k/coldfire/
Dstmark2.c25 .size = 0x100000,
26 .offset = 0x0
29 .size = 0x700000,
49 .bus_num = 0,
56 /* SPI controller data, SPI (0) */
59 .bus_num = 0,
65 [0] = {
67 .end = MCFDSPI_BASE0 + 0xFF,
87 .id = 0,
107 __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL); in init_stmark2()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv04.c36 0x0040053c,
37 0x00400544,
38 0x00400540,
39 0x00400548,
48 0x00400184,
49 0x004001a4,
50 0x004001c4,
51 0x004001e4,
52 0x00400188,
53 0x004001a8,
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv04.c36 0x0040053c,
37 0x00400544,
38 0x00400540,
39 0x00400548,
48 0x00400184,
49 0x004001a4,
50 0x004001c4,
51 0x004001e4,
52 0x00400188,
53 0x004001a8,
[all …]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/goya/asic_reg/
Dmmu_masks.h23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
39 #define MMU_MMU_ENABLE_R_SHIFT 0
40 #define MMU_MMU_ENABLE_R_MASK 0x1
[all …]

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