Searched +full:0 +full:x820 (Results 1 – 25 of 282) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/i2c/busses/ |
| D | scx200_acb.rst | 15 By default the driver uses two base addresses 0x820 and 0x840.
16 If you want only one base address, specify the second as 0 so as to
28 The SC1100 WRAP boards are known to use base addresses 0x810 and 0x820.
32 scx200_acb.base=0x810,0x820
37 options scx200_acb base=0x810,0x820
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| /kernel/linux/linux-6.6/Documentation/i2c/busses/ |
| D | scx200_acb.rst | 15 By default the driver uses two base addresses 0x820 and 0x840.
16 If you want only one base address, specify the second as 0 so as to
28 The SC1100 WRAP boards are known to use base addresses 0x810 and 0x820.
32 scx200_acb.base=0x810,0x820
37 options scx200_acb base=0x810,0x820
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| /kernel/linux/linux-6.6/arch/arm/mm/ |
| D | cache-tauros3.h | 20 #define TAUROS3_EVENT_CNT2_CFG 0x224
21 #define TAUROS3_EVENT_CNT2_VAL 0x228
22 #define TAUROS3_INV_ALL 0x780
23 #define TAUROS3_CLEAN_ALL 0x784
24 #define TAUROS3_AUX2_CTRL 0x820
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | cache-tauros3.h | 20 #define TAUROS3_EVENT_CNT2_CFG 0x224
21 #define TAUROS3_EVENT_CNT2_VAL 0x228
22 #define TAUROS3_INV_ALL 0x780
23 #define TAUROS3_CLEAN_ALL 0x784
24 #define TAUROS3_AUX2_CTRL 0x820
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | toshiba,tmpv770x-pipllct.yaml | 43 #clock-cells = <0>;
52 reg = <0 0x24220000 0 0x820>;
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | npcm_wdt.c | 15 #define NPCM_WTCR 0x1C
24 #define NPCM_WTR BIT(0) /* Reset counter */
29 * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
30 * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
31 * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
32 * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
33 * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
34 * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
35 * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
36 * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
[all …]
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| /kernel/linux/linux-6.6/drivers/watchdog/ |
| D | npcm_wdt.c | 16 #define NPCM_WTCR 0x1C
25 #define NPCM_WTR BIT(0) /* Reset counter */
30 * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
31 * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
32 * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
33 * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
34 * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
35 * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
36 * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
37 * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/ |
| D | bcm4908_enet.h | 5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
[all …]
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| /kernel/linux/linux-6.6/drivers/staging/rtl8192u/ |
| D | r819xU_phyreg.h | 5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8192u/ |
| D | r819xU_phyreg.h | 5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
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| /kernel/linux/linux-5.10/include/dt-bindings/pinctrl/ |
| D | am33xx.h | 18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
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| /kernel/linux/linux-6.6/include/dt-bindings/pinctrl/ |
| D | am33xx.h | 18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-fman3-1.dtsi | 2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x820 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
56 reg = <0x82000 0x1000>;
60 cell-index = <0x3>;
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-fman3-1.dtsi | 2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x820 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
56 reg = <0x82000 0x1000>;
60 cell-index = <0x3>;
[all …]
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| /kernel/linux/linux-6.6/include/linux/usb/ |
| D | usb338x.h | 19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-miphy28lp.txt | 56 reg = <0x9b22000 0xff>,
57 <0x9b09000 0xff>,
58 <0x9b04000 0xff>;
63 st,syscfg = <0x114 0x818 0xe0 0xec>;
71 reg = <0x9b2a000 0xff>,
72 <0x9b19000 0xff>,
73 <0x9b14000 0xff>;
78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
87 reg = <0x8f95000 0xff>,
88 <0x8f90000 0xff>;
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | phy-miphy28lp.txt | 56 reg = <0x9b22000 0xff>,
57 <0x9b09000 0xff>,
58 <0x9b04000 0xff>;
63 st,syscfg = <0x114 0x818 0xe0 0xec>;
71 reg = <0x9b2a000 0xff>,
72 <0x9b19000 0xff>,
73 <0x9b14000 0xff>;
78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
87 reg = <0x8f95000 0xff>,
88 <0x8f90000 0xff>;
[all …]
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| /kernel/linux/linux-5.10/include/linux/usb/ |
| D | usb338x.h | 30 #define SCRATCH 0x0b
47 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
49 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
56 #define DEVICE_CLASS 0
59 #define U1_SYSTEM_EXIT_LATENCY 0
62 #define U1_DEVICE_EXIT_LATENCY 0
66 #define USB_L1_LPM_SUPPORT 0
69 #define BEST_EFFORT_LATENCY_TOLERANCE 0
77 #define SERIAL_NUMBER_STRING_ENABLE 0
90 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/rsi/ |
| D | rsi_hal.h | 45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/rsi/ |
| D | rsi_hal.h | 45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/ |
| D | qcom,sm6375-mdss.yaml | 44 "^display-controller@[0-9a-f]+$":
50 "^dsi@[0-9a-f]+$":
58 "^phy@[0-9a-f]+$":
76 reg = <0x05e00000 0x1000>;
90 iommus = <&apps_smmu 0x820 0x2>;
97 reg = <0x05e01000 0x8e030>,
98 <0x05eb0000 0x2008>;
123 interrupts = <0>;
127 #size-cells = <0>;
129 port@0 {
[all …]
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| /kernel/linux/linux-6.6/drivers/soc/imx/ |
| D | soc-imx.c | 16 #define IIM_UID 0x820
18 #define OCOTP_UID_H 0x420
19 #define OCOTP_UID_L 0x410
21 #define OCOTP_ULP_UID_1 0x4b0
22 #define OCOTP_ULP_UID_2 0x4c0
23 #define OCOTP_ULP_UID_3 0x4d0
24 #define OCOTP_ULP_UID_4 0x4e0
34 u64 soc_uid = 0; in imx_soc_device_init()
41 return 0; in imx_soc_device_init()
155 soc_uid = val & 0xffff; in imx_soc_device_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/reset/sti/ |
| D | reset-stih407.c | 25 /* Powerdown requests control 0 */
26 #define SYSCFG_5000 0x0
27 #define SYSSTAT_5500 0x7d0
29 #define SYSCFG_5001 0x4
30 #define SYSSTAT_5501 0x7d4
33 #define SYSCFG_4032 0x80
34 #define SYSSTAT_4520 0x820
35 #define SYSCFG_4002 0x8
39 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
46 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
[all …]
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| /kernel/linux/linux-6.6/drivers/reset/sti/ |
| D | reset-stih407.c | 25 /* Powerdown requests control 0 */
26 #define SYSCFG_5000 0x0
27 #define SYSSTAT_5500 0x7d0
29 #define SYSCFG_5001 0x4
30 #define SYSSTAT_5501 0x7d4
33 #define SYSCFG_4032 0x80
34 #define SYSSTAT_4520 0x820
35 #define SYSCFG_4002 0x8
39 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
46 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
[all …]
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| /kernel/linux/linux-5.10/drivers/reset/hisilicon/ |
| D | hi6220_reset.c | 23 #define PERIPH_ASSERT_OFFSET 0x300
24 #define PERIPH_DEASSERT_OFFSET 0x304
25 #define PERIPH_MAX_INDEX 0x509
27 #define SC_MEDIA_RSTEN 0x052C
28 #define SC_MEDIA_RSTDIS 0x0530
50 u32 offset = idx & 0xff; in hi6220_peripheral_assert()
51 u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10; in hi6220_peripheral_assert()
62 u32 offset = idx & 0xff; in hi6220_peripheral_deassert()
63 u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10; in hi6220_peripheral_deassert()
96 #define AO_SCTRL_SC_PW_CLKEN0 0x800
[all …]
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