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Searched +full:0 +full:x92400000 (Results 1 – 8 of 8) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dsp/
Dfsl,dsp.yaml155 reg = <0x596e8000 0x88000>;
165 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
171 reg = <0x92400000 0x1000000>;
175 reg = <0x942f0000 0x8000>;
179 reg = <0x942f8000 0x8000>;
184 reg = <0x94300000 0x100000>;
190 reg = <0x3b6e8000 0x88000>;
199 mboxes = <&mu2 0 0>,
200 <&mu2 1 0>,
201 <&mu2 3 0>;
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8dxl.dtsi35 #size-cells = <0>;
38 A35_0: cpu@0 {
41 reg = <0x0 0x0>;
52 reg = <0x0 0x1>;
87 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
88 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
100 reg = <0 0x92400000 0 0x2000000>;
120 mboxes = <&lsio_mu1 0 0
121 &lsio_mu1 1 0
152 reg = <0x2c4 6>;
[all …]
Dimx8qxp.dtsi56 #size-cells = <0>;
59 A35_0: cpu@0 {
62 reg = <0x0 0x0>;
64 i-cache-size = <0x8000>;
67 d-cache-size = <0x8000>;
79 reg = <0x0 0x1>;
81 i-cache-size = <0x8000>;
84 d-cache-size = <0x8000>;
96 reg = <0x0 0x2>;
98 i-cache-size = <0x8000>;
[all …]
Dimx8-apalis-v1.1.dtsi17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18 brightness-levels = <0 45 63 88 119 158 203 255>;
28 pinctrl-0 = <&pinctrl_gpio8>;
30 gpio-fan,speed-map = < 0 0
82 pinctrl-0 = <&pinctrl_wifi_pdn>;
93 pinctrl-0 = <&pinctrl_gpio7>;
105 pinctrl-0 = <&pinctrl_usbh_en>;
135 reg = <0 0x84000000 0 0x2000000>;
140 reg = <0 0x86000000 0 0x200000>;
145 reg = <0 0x86200000 0 0x200000>;
[all …]
Dimx8mp.dtsi48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8qxp.dtsi52 #size-cells = <0>;
55 A35_0: cpu@0 {
58 reg = <0x0 0x0>;
69 reg = <0x0 0x1>;
80 reg = <0x0 0x2>;
91 reg = <0x0 0x3>;
124 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
125 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
137 reg = <0 0x92400000 0 0x2000000>;
157 mboxes = <&lsio_mu1 0 0
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dmsm8996-xiaomi-common.dtsi17 #clock-cells = <0>;
21 pinctrl-0 = <&divclk1_default>;
26 #clock-cells = <0>;
31 pinctrl-0 = <&divclk4_pin_a>;
59 pinctrl-0 = <&irled_default>;
64 reg = <0x0 0x88800000 0x0 0x1400000>;
68 /* This platform has all PIL regions offset by 0x1400000 */
71 reg = <0x0 0x89c00000 0x0 0x6200000>;
77 reg = <0x0 0x8fe00000 0x0 0x1b00000>;
83 reg = <0x0 0x91900000 0x0 0xa00000>;
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/
D0001_linux_arch.patch116 @@ -0,0 +1,8 @@
130 @@ -0,0 +1,672 @@
143 + ranges = <0x59000000 0x0 0x59000000 0x1000000>;
147 + #clock-cells = <0>;
154 + reg = <0x591f0000 0x10000>,
155 + <0x59200000 0x10000>, /* asrc0 */
156 + <0x59210000 0x10000>,
157 + <0x59220000 0x10000>,
158 + <0x59230000 0x10000>,
159 + <0x59240000 0x10000>,
[all …]