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/kernel/linux/linux-6.6/drivers/pinctrl/mediatek/
Dpinctrl-mt8516.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
34 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
Dpinctrl-mt8167.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
34 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt8167.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
Dpinctrl-mt8516.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/netlogic/
Dxlp_evp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
Dxlp_svp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
Dxlp_fvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x37100 0x20>;
54 #size-cells = <0>;
55 reg = <0 0x37120 0x20>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dpm8550vs.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
34 polling-delay = <0>;
41 hysteresis = <0>;
47 hysteresis = <0>;
55 polling-delay = <0>;
62 hysteresis = <0>;
68 hysteresis = <0>;
76 polling-delay = <0>;
[all …]
Dsa8775p-pmics.dtsi11 pmm8654au_0_thermal: pm8775-0-thermal {
13 polling-delay = <0>;
19 hysteresis = <0>;
25 hysteresis = <0>;
33 polling-delay = <0>;
39 hysteresis = <0>;
45 hysteresis = <0>;
53 polling-delay = <0>;
59 hysteresis = <0>;
65 hysteresis = <0>;
[all …]
Dpmr735d.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
34 polling-delay = <0>;
41 hysteresis = <0>;
47 hysteresis = <0>;
59 reg = <0xa SPMI_USID>;
61 #size-cells = <0>;
65 reg = <0xa00>;
66 interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
[all …]
Dsc8280xp-pmics.dtsi14 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
34 polling-delay = <0>;
40 hysteresis = <0>;
46 hysteresis = <0>;
55 pmk8280: pmic@0 {
57 reg = <0x0 SPMI_USID>;
59 #size-cells = <0>;
63 reg = <0x1300>, <0x800>;
[all …]
Dpm8550ve.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
38 reg = <0x5 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0xa00>;
45 interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
46 #thermal-sensor-cells = <0>;
51 reg = <0x8800>;
53 gpio-ranges = <&pm8550ve_gpios 0 0 8>;
Dpm8450.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
38 reg = <0x7 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0xa00>;
45 interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
46 #thermal-sensor-cells = <0>;
51 reg = <0x8800>;
53 gpio-ranges = <&pm8450_gpios 0 0 4>;
Dpm8550b.dtsi13 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
38 reg = <0x7 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0xa00>;
45 interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
46 #thermal-sensor-cells = <0>;
51 reg = <0x8800>;
53 gpio-ranges = <&pm8550b_gpios 0 0 12>;
[all …]
Dpm8350b.dtsi13 polling-delay = <0>;
19 hysteresis = <0>;
25 hysteresis = <0>;
36 reg = <0x3 SPMI_USID>;
38 #size-cells = <0>;
42 reg = <0xa00>;
43 interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
44 #thermal-sensor-cells = <0>;
49 reg = <0x8800>;
51 gpio-ranges = <&pm8350b_gpios 0 0 8>;
Dpm8350.dtsi13 polling-delay = <0>;
19 hysteresis = <0>;
25 hysteresis = <0>;
36 reg = <0x1 SPMI_USID>;
38 #size-cells = <0>;
42 reg = <0xa00>;
43 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
44 #thermal-sensor-cells = <0>;
49 reg = <0x8800>;
51 gpio-ranges = <&pm8350_gpios 0 0 10>;
Dpmr735a.dtsi12 reg = <0x4 SPMI_USID>;
14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pmr735a_gpios 0 0 4>;
39 polling-delay = <0>;
45 hysteresis = <0>;
51 hysteresis = <0>;
/kernel/linux/linux-5.10/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_reg.h11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
14 /* 3. RF register 0x00-2E */
19 /* 3. Page8(0x800) */
20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
23 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
24 #define rFPGA0_XA_HSSIParameter2 0x824
25 #define rFPGA0_XB_HSSIParameter1 0x828
26 #define rFPGA0_XB_HSSIParameter2 0x82c
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos.h20 #define EXYNOS_GPIO_ECON_OFFSET 0x700
21 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
22 #define EXYNOS_GPIO_EMASK_OFFSET 0x900
23 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00
24 #define EXYNOS_WKUP_ECON_OFFSET 0xE00
25 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
26 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
27 #define EXYNOS7_WKUP_ECON_OFFSET 0x700
28 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
29 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/samsung/
Dpinctrl-exynos.h20 #define EXYNOS_PIN_CON_FUNC_EINT 0xf
23 #define EXYNOS_GPIO_ECON_OFFSET 0x700
24 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
25 #define EXYNOS_GPIO_EMASK_OFFSET 0x900
26 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00
27 #define EXYNOS_WKUP_ECON_OFFSET 0xE00
28 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
29 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
30 #define EXYNOS7_WKUP_ECON_OFFSET 0x700
31 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/sirf/
Dpinctrl-atlas7.c30 #define N 0
33 #define BANK_DS 0
36 #define CLR_REG(r) ((r) + 0x04)
39 #define FUNC_CLEAR_MASK 0x7
40 #define FUNC_GPIO 0
41 #define FUNC_ANALOGUE 0x8
42 #define ANA_CLEAR_MASK 0x1
46 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
60 #define DS0 BIT(0)
61 #define DSZ 0
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/
Dpmx65.dtsi14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pmx65_gpios 0 0 16>;
/kernel/linux/linux-5.10/arch/openrisc/mm/
Dinit.c47 unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 }; in zone_sizes_init()
109 for (j = 0; p < e && j < PTRS_PER_PTE; in map_ram()
123 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__, in map_ram()
139 for (i = 0; i < PTRS_PER_PGD; i++) in paging_init()
140 swapper_pg_dir[i] = __pgd(0); in paging_init()
164 unsigned long *dtlb_vector = __va(0x900); in paging_init()
165 unsigned long *itlb_vector = __va(0xa00); in paging_init()
188 mtspr(SPR_ICBIR, 0x900); in paging_init()
189 mtspr(SPR_ICBIR, 0xa00); in paging_init()
209 memset((void *)empty_zero_page, 0, PAGE_SIZE); in mem_init()
/kernel/linux/linux-6.6/arch/openrisc/mm/
Dinit.c43 unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 }; in zone_sizes_init()
105 for (j = 0; p < e && j < PTRS_PER_PTE; in map_ram()
119 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__, in map_ram()
132 for (i = 0; i < PTRS_PER_PGD; i++) in paging_init()
133 swapper_pg_dir[i] = __pgd(0); in paging_init()
155 unsigned long *dtlb_vector = __va(0x900); in paging_init()
156 unsigned long *itlb_vector = __va(0xa00); in paging_init()
179 mtspr(SPR_ICBIR, 0x900); in paging_init()
180 mtspr(SPR_ICBIR, 0xa00); in paging_init()
200 memset((void *)empty_zero_page, 0, PAGE_SIZE); in mem_init()
/kernel/linux/linux-6.6/drivers/clk/rockchip/
Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
[all …]

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