Searched +full:0 +full:xab0000 (Results 1 – 8 of 8) sorted by relevance
40 SDHC System Operation Control Register Bit[7:0].61 Valid range = [0:0x1F].62 ZNR is set as 0xF by default if this property is not provided.67 Valid range = [0:0x1F].68 ZPR is set as 0xF by default if this property is not provided.74 Set as 0x4 by default if this property is not provided.92 be set as 0x9 in driver.109 reg = <0xaa0000 0x1000>;127 reg = <0xab0000 0x1000>;141 reg = <0xaa0000 0x1000>,[all …]
64 minimum: 068 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to89 minimum: 090 maximum: 0x1f91 default: 0xf98 minimum: 099 maximum: 0x1f100 default: 0xf109 default: 0x4131 default: 0x9[all …]
28 #size-cells = <0>;31 cpu@0 {35 reg = <0>;68 #clock-cells = <0>;78 ranges = <0 0xf7000000 0x1000000>;82 reg = <0xab0000 0x200>;91 reg = <0xab0800 0x200>;100 reg = <0xab1000 0x200>;104 pinctrl-0 = <&emmc_pmux>;111 reg = <0xac0000 0x1000>;[all …]
27 #size-cells = <0>;29 cpu: cpu@0 {33 reg = <0>;53 #clock-cells = <0>;63 ranges = <0 0xf7000000 0x1000000>;67 reg = <0xab0000 0x200>;76 reg = <0xac0000 0x1000>;83 reg = <0xad0000 0x100>;88 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;95 reg = <0xad0200 0x20>;[all …]
22 #size-cells = <0>;25 cpu0: cpu@0 {29 reg = <0>;113 #clock-cells = <0>;122 ranges = <0 0xf7000000 0x1000000>;127 reg = <0xab0000 0x200>;136 reg = <0xab0800 0x200>;145 reg = <0xab1000 0x200>;154 reg = <0xac0000 0x1000>;163 reg = <0xad0000 0x58>;[all …]