Home
last modified time | relevance | path

Searched +full:0 +full:xd0000 (Results 1 – 25 of 104) sorted by relevance

12345

/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/cfg/
Dsc.c19 #define IWL_SC_NVM_VERSION 0x0a1d
22 #define IWL_SC_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_SC_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_SC_DCCM2_OFFSET 0x880000
25 #define IWL_SC_DCCM2_LEN 0x8000
26 #define IWL_SC_SMEM_OFFSET 0x400000
27 #define IWL_SC_SMEM_LEN 0xD0000
79 .mac_addr_from_csr = 0x30, \
85 .min_umac_error_event_table = 0xD0000, \
86 .d3_debug_data_base_addr = 0x401000, \
[all …]
Dbz.c19 #define IWL_BZ_NVM_VERSION 0x0a1d
22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_BZ_DCCM2_OFFSET 0x880000
25 #define IWL_BZ_DCCM2_LEN 0x8000
26 #define IWL_BZ_SMEM_OFFSET 0x400000
27 #define IWL_BZ_SMEM_LEN 0xD0000
82 .mac_addr_from_csr = 0x30, \
88 .min_umac_error_event_table = 0xD0000, \
89 .d3_debug_data_base_addr = 0x401000, \
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Dkirkwood-t5325.dts23 reg = <0x00000000 0x20000000>;
33 pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
76 flash@0 {
81 reg = <0>;
82 mode = <0>;
84 partition@0 {
85 reg = <0x0 0x80000>;
90 reg = <0x80000 0x40000>;
95 reg = <0xc0000 0x10000>;
100 reg = <0xd0000 0x10000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dkirkwood-t5325.dts23 reg = <0x00000000 0x20000000>;
33 pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
76 flash@0 {
81 reg = <0>;
82 mode = <0>;
84 partition@0 {
85 reg = <0x0 0x80000>;
90 reg = <0x80000 0x40000>;
95 reg = <0xc0000 0x10000>;
100 reg = <0xd0000 0x10000>;
[all …]
Dbcm53340-ubnt-unifi-switch8.dts22 memory@0 {
24 reg = <0x00000000 0x08000000>,
25 <0x68000000 0x08000000>;
35 bspi-sel = <0>;
37 flash: m25p80@0 {
39 reg = <0>;
46 partition@0 {
48 reg = <0x0 0xc0000>;
53 reg = <0xc0000 0x10000>;
58 reg = <0xd0000 0x10000>;
[all …]
/kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/
Dstr2mem_defs.h19 #define _STR2MEM_CRUN_BIT 0x100000
20 #define _STR2MEM_CMD_BITS 0x0F0000
21 #define _STR2MEM_COUNT_BITS 0x00FFFF
23 #define _STR2MEM_BLOCKS_CMD 0xA0000
24 #define _STR2MEM_PACKETS_CMD 0xB0000
25 #define _STR2MEM_BYTES_CMD 0xC0000
26 #define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000
28 #define _STR2MEM_SOFT_RESET_REG_ID 0
/kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/
Dstr2mem_defs.h19 #define _STR2MEM_CRUN_BIT 0x100000
20 #define _STR2MEM_CMD_BITS 0x0F0000
21 #define _STR2MEM_COUNT_BITS 0x00FFFF
23 #define _STR2MEM_BLOCKS_CMD 0xA0000
24 #define _STR2MEM_PACKETS_CMD 0xB0000
25 #define _STR2MEM_BYTES_CMD 0xC0000
26 #define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000
28 #define _STR2MEM_SOFT_RESET_REG_ID 0
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm53340-ubnt-unifi-switch8.dts22 memory@0 {
24 reg = <0x00000000 0x08000000>,
25 <0x68000000 0x08000000>;
35 bspi-sel = <0>;
37 flash: flash@0 {
39 reg = <0>;
46 partition@0 {
48 reg = <0x0 0xc0000>;
53 reg = <0xc0000 0x10000>;
58 reg = <0xd0000 0x10000>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/dove/
Dpmu.txt24 - #power-domain-cells: must be 0.
35 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
43 #power-domain-cells = <0>;
44 marvell,pmu_pwr_mask = <0x00000008>;
45 marvell,pmu_iso_mask = <0x00000001>;
50 #power-domain-cells = <0>;
51 marvell,pmu_pwr_mask = <0x00000004>;
52 marvell,pmu_iso_mask = <0x00000002>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/dove/
Dpmu.txt24 - #power-domain-cells: must be 0.
35 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
43 #power-domain-cells = <0>;
44 marvell,pmu_pwr_mask = <0x00000008>;
45 marvell,pmu_iso_mask = <0x00000001>;
50 #power-domain-cells = <0>;
51 marvell,pmu_pwr_mask = <0x00000004>;
52 marvell,pmu_iso_mask = <0x00000002>;
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx7-mba7.dtsi25 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
35 button-0 {
201 pinctrl-0 = <&pinctrl_ecspi1>;
202 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
209 pinctrl-0 = <&pinctrl_ecspi2>;
215 pinctrl-0 = <&pinctrl_enet1>;
226 #size-cells = <0>;
228 ethphy1_0: ethernet-phy@0 {
230 reg = <0>;
245 uboot@0 {
[all …]
/kernel/linux/linux-6.6/Documentation/sound/cards/
Dmultisound.sh77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card
96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary
107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil
108 # synth to 0x330 and irq 9 (may need editing for your system):
110 # (READPORT 0x0203)
115 # (CONFIGURE BVJ0440/-1 (LD 0
116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000))
121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E)))
140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it
143 # on the card to 0x250, 0x260 or 0x270).
[all …]
/kernel/linux/linux-5.10/Documentation/sound/cards/
Dmultisound.sh77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card
96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary
107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil
108 # synth to 0x330 and irq 9 (may need editing for your system):
110 # (READPORT 0x0203)
115 # (CONFIGURE BVJ0440/-1 (LD 0
116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000))
121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E)))
140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it
143 # on the card to 0x250, 0x260 or 0x270).
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-dove/
Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-dove/
Ddove.h19 * e0000000 @runtime 128M PCIe-0 Memory space
23 * f2000000 fee00000 1M PCIe-0 I/O space
27 #define DOVE_CESA_PHYS_BASE 0xc8000000
28 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
31 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
34 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
37 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
40 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
44 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dmarvell,nand-controller.yaml66 minimum: 0
71 - minimum: 0
156 reg = <0xd0000 0x54>;
158 #size-cells = <0>;
160 clocks = <&coredivclk 0>;
162 nand@0 {
163 reg = <0>;
165 nand-rb = <0>;
177 partition@0 {
179 reg = <0x00000000 0x40000000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dmarvell-nand.txt15 - #size-cells: shall be set to 0.
38 - reg: shall contain the native Chip Select ids (0-3).
39 - nand-rb: see nand-controller.yaml (0-1).
68 reg = <0xd0000 0x54>;
70 #size-cells = <0>;
72 clocks = <&coredivclk 0>;
74 nand@0 {
75 reg = <0>;
77 nand-rb = <0>;
89 partition@0 {
[all …]
/kernel/linux/linux-5.10/Documentation/networking/
Dgeneric-hdlc.rst140 insmod n2 hw=0x300,10,0xD0000,01
148 insmod c101 hw=9,0xdc000
/kernel/linux/linux-6.6/Documentation/networking/
Dgeneric-hdlc.rst140 insmod n2 hw=0x300,10,0xD0000,01
148 insmod c101 hw=9,0xdc000
/kernel/linux/linux-6.6/arch/arm/mach-imx/
Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
Dsun8i_mixer.h18 #define SUN8I_MIXER_GLOBAL_CTL 0x0
19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
27 #define DE2_MIXER_UNIT_SIZE 0x6000
28 #define DE3_MIXER_UNIT_SIZE 0x3000
30 #define DE2_BLD_BASE 0x1000
31 #define DE2_CH_BASE 0x2000
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/
Dsun8i_mixer.h18 #define SUN8I_MIXER_GLOBAL_CTL 0x0
19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
27 #define DE2_MIXER_UNIT_SIZE 0x6000
28 #define DE3_MIXER_UNIT_SIZE 0x3000
30 #define DE2_BLD_BASE 0x1000
31 #define DE2_CH_BASE 0x2000
[all …]

12345