Home
last modified time | relevance | path

Searched +full:0 +full:xd8000 (Results 1 – 25 of 45) sorted by relevance

12

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/dove/
Dpmu.txt24 - #power-domain-cells: must be 0.
35 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
43 #power-domain-cells = <0>;
44 marvell,pmu_pwr_mask = <0x00000008>;
45 marvell,pmu_iso_mask = <0x00000001>;
50 #power-domain-cells = <0>;
51 marvell,pmu_pwr_mask = <0x00000004>;
52 marvell,pmu_iso_mask = <0x00000002>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/dove/
Dpmu.txt24 - #power-domain-cells: must be 0.
35 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
43 #power-domain-cells = <0>;
44 marvell,pmu_pwr_mask = <0x00000008>;
45 marvell,pmu_iso_mask = <0x00000001>;
50 #power-domain-cells = <0>;
51 marvell,pmu_pwr_mask = <0x00000004>;
52 marvell,pmu_iso_mask = <0x00000002>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.yaml83 reg = <0xd4280800 0x800>;
95 reg = <0xd8000 0x1000>,
96 <0xdc000 0x100>,
97 <0x18454 0x4>;
98 interrupts = <0 25 0x4>;
101 mrvl,clk-delay-cycles = <0x1F>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.yaml73 pinctrl-0:
99 reg = <0xd4280800 0x800>;
111 reg = <0xd8000 0x1000>,
112 <0xdc000 0x100>,
113 <0x18454 0x4>;
114 interrupts = <0 25 0x4>;
117 mrvl,clk-delay-cycles = <0x1F>;
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/goya/asic_reg/
Dmme_qm_regs.h22 #define mmMME_QM_GLBL_CFG0 0xD8000
24 #define mmMME_QM_GLBL_CFG1 0xD8004
26 #define mmMME_QM_GLBL_PROT 0xD8008
28 #define mmMME_QM_GLBL_ERR_CFG 0xD800C
30 #define mmMME_QM_GLBL_ERR_ADDR_LO 0xD8010
32 #define mmMME_QM_GLBL_ERR_ADDR_HI 0xD8014
34 #define mmMME_QM_GLBL_ERR_WDATA 0xD8018
36 #define mmMME_QM_GLBL_SECURE_PROPS 0xD801C
38 #define mmMME_QM_GLBL_NON_SECURE_PROPS 0xD8020
40 #define mmMME_QM_GLBL_STS0 0xD8024
[all …]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/
Dmme_qm_regs.h22 #define mmMME_QM_GLBL_CFG0 0xD8000
24 #define mmMME_QM_GLBL_CFG1 0xD8004
26 #define mmMME_QM_GLBL_PROT 0xD8008
28 #define mmMME_QM_GLBL_ERR_CFG 0xD800C
30 #define mmMME_QM_GLBL_ERR_ADDR_LO 0xD8010
32 #define mmMME_QM_GLBL_ERR_ADDR_HI 0xD8014
34 #define mmMME_QM_GLBL_ERR_WDATA 0xD8018
36 #define mmMME_QM_GLBL_SECURE_PROPS 0xD801C
38 #define mmMME_QM_GLBL_NON_SECURE_PROPS 0xD8020
40 #define mmMME_QM_GLBL_STS0 0xD8024
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-imx/
Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
Dsun8i_mixer.h18 #define SUN8I_MIXER_GLOBAL_CTL 0x0
19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
27 #define DE2_MIXER_UNIT_SIZE 0x6000
28 #define DE3_MIXER_UNIT_SIZE 0x3000
30 #define DE2_BLD_BASE 0x1000
31 #define DE2_CH_BASE 0x2000
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/
Dsun8i_mixer.h18 #define SUN8I_MIXER_GLOBAL_CTL 0x0
19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
27 #define DE2_MIXER_UNIT_SIZE 0x6000
28 #define DE3_MIXER_UNIT_SIZE 0x3000
30 #define DE2_BLD_BASE 0x1000
31 #define DE2_CH_BASE 0x2000
[all …]
/kernel/linux/linux-6.6/Documentation/sound/cards/
Dmultisound.sh77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card
96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary
107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil
108 # synth to 0x330 and irq 9 (may need editing for your system):
110 # (READPORT 0x0203)
115 # (CONFIGURE BVJ0440/-1 (LD 0
116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000))
121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E)))
140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it
143 # on the card to 0x250, 0x260 or 0x270).
[all …]
/kernel/linux/linux-5.10/Documentation/sound/cards/
Dmultisound.sh77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card
96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary
107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil
108 # synth to 0x330 and irq 9 (may need editing for your system):
110 # (READPORT 0x0203)
115 # (CONFIGURE BVJ0440/-1 (LD 0
116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000))
121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E)))
140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it
143 # on the card to 0x250, 0x260 or 0x270).
[all …]
/kernel/linux/linux-5.10/sound/isa/msnd/
Dmsnd_pinnacle.c94 snd_msnd_DAPQ(chip, 0); in snd_msnd_eval_dsp_msg()
99 chip->playDMAPos = 0; in snd_msnd_eval_dsp_msg()
110 chip->captureDMAPos = 0; in snd_msnd_eval_dsp_msg()
137 ": DSP message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
149 snd_printd(KERN_WARNING LOGNAME ": HIMT message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
173 head = 0; in snd_msnd_interrupt()
195 while (timeout-- > 0) { in snd_msnd_reset_dsp()
197 return 0; in snd_msnd_reset_dsp()
220 if (snd_msnd_reset_dsp(chip->io, &info) < 0) { in snd_msnd_probe()
229 "I/O 0x%lx-0x%lx, IRQ %d, memory mapped to 0x%lX-0x%lX\n", in snd_msnd_probe()
[all …]
/kernel/linux/linux-6.6/sound/isa/msnd/
Dmsnd_pinnacle.c94 snd_msnd_DAPQ(chip, 0); in snd_msnd_eval_dsp_msg()
99 chip->playDMAPos = 0; in snd_msnd_eval_dsp_msg()
110 chip->captureDMAPos = 0; in snd_msnd_eval_dsp_msg()
137 ": DSP message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
149 snd_printd(KERN_WARNING LOGNAME ": HIMT message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
173 head = 0; in snd_msnd_interrupt()
195 while (timeout-- > 0) { in snd_msnd_reset_dsp()
197 return 0; in snd_msnd_reset_dsp()
220 if (snd_msnd_reset_dsp(chip->io, &info) < 0) { in snd_msnd_probe()
229 "I/O 0x%lx-0x%lx, IRQ %d, memory mapped to 0x%lX-0x%lX\n", in snd_msnd_probe()
[all …]
/kernel/linux/linux-5.10/drivers/soc/dove/
Dpmu.c22 #define PMC_SW_RST 0x30
23 #define PMC_IRQ_CAUSE 0x50
24 #define PMC_IRQ_MASK 0x54
26 #define PMU_PWR 0x10
27 #define PMU_ISO 0x58
60 return 0; in pmu_reset_reset()
74 return 0; in pmu_reset_assert()
88 return 0; in pmu_reset_deassert()
174 return 0; in pmu_domain_power_off()
208 return 0; in pmu_domain_power_on()
[all …]
/kernel/linux/linux-6.6/drivers/soc/dove/
Dpmu.c22 #define PMC_SW_RST 0x30
23 #define PMC_IRQ_CAUSE 0x50
24 #define PMC_IRQ_MASK 0x54
26 #define PMU_PWR 0x10
27 #define PMU_ISO 0x58
60 return 0; in pmu_reset_reset()
74 return 0; in pmu_reset_assert()
88 return 0; in pmu_reset_deassert()
174 return 0; in pmu_domain_power_off()
208 return 0; in pmu_domain_power_on()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
Dregs.h8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x8000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
25 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
27 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
42 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0>;
80 /* 32M internal register @ 0xd000_0000 */
81 ranges = <0x0 0x0 0xd0000000 0x2000000>;
85 reg = <0x8300 0x40>;
93 reg = <0xd000 0x1000>;
99 #size-cells = <0>;
100 reg = <0x10600 0xA00>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7915/
Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
Ddove.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7996/
Dregs.h42 #define MT_MCU_INT_EVENT 0x2108
43 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
48 #define MT_PLE_BASE 0x820c0000
51 #define MT_FL_Q_EMPTY MT_PLE(0x360)
52 #define MT_FL_Q0_CTRL MT_PLE(0x3e0)
53 #define MT_FL_Q2_CTRL MT_PLE(0x3e8)
54 #define MT_FL_Q3_CTRL MT_PLE(0x3ec)
56 #define MT_PLE_FREEPG_CNT MT_PLE(0x380)
57 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384)
58 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c)
[all …]

12