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/kernel/linux/linux-6.6/drivers/gpu/drm/display/
Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
34 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
48 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
49 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
54 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
56 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
81 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
109 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
110 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
111 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
[all …]
/kernel/linux/linux-6.6/arch/powerpc/crypto/
Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
Daes-gcm-p10.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 # Accelerated AES-GCM stitched implementation for ppc64le.
5 # Copyright 2022- IBM Inc. All rights reserved
22 # Hash keys = v3 - v14
29 # v31 - counter 1
32 # vs0 - vs14 for round keys
35 # This implementation uses stitched AES-GCM approach to improve overall performance.
48 # v15 - v18 - input states
49 # vs1 - vs9 - round keys
59 vcipher 17, 17, 19
[all …]
Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
15 # 2. c += d; b ^= c; b <<<= 12;
20 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 12
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
86 SAVE_GPR 17, 136, 1
119 SAVE_VSX 17, 240, 9
154 RESTORE_VSX 17, 240, 9
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/stm32/
Dpinctrl-stm32mp135.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
10 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH1_MII_CRS"),
24 STM32_FUNCTION(17, "ANALOG")
35 STM32_FUNCTION(12, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
36 STM32_FUNCTION(17, "ANALOG")
46 STM32_FUNCTION(12, "ETH1_MDIO"),
47 STM32_FUNCTION(17, "ANALOG")
59 STM32_FUNCTION(12, "ETH1_MII_COL"),
[all …]
Dpinctrl-stm32h743.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
24 STM32_FUNCTION(12, "ETH_MII_CRS"),
26 STM32_FUNCTION(17, "ANALOG")
39 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
42 STM32_FUNCTION(17, "ANALOG")
53 STM32_FUNCTION(12, "ETH_MDIO"),
57 STM32_FUNCTION(17, "ANALOG")
69 STM32_FUNCTION(12, "ETH_MII_COL"),
72 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32f769.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH_MII_CRS"),
24 STM32_FUNCTION(17, "ANALOG")
35 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
38 STM32_FUNCTION(17, "ANALOG")
48 STM32_FUNCTION(12, "ETH_MDIO"),
52 STM32_FUNCTION(17, "ANALOG")
63 STM32_FUNCTION(12, "ETH_MII_COL"),
66 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32mp157.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
10 #include "pinctrl-stm32.h"
25 STM32_FUNCTION(12, "ETH1_GMII_CRS ETH1_MII_CRS"),
27 STM32_FUNCTION(17, "ANALOG")
42 STM32_FUNCTION(12, "ETH1_GMII_RX_CLK ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
45 STM32_FUNCTION(17, "ANALOG")
58 STM32_FUNCTION(12, "ETH1_MDIO"),
62 STM32_FUNCTION(17, "ANALOG")
74 STM32_FUNCTION(12, "ETH1_GMII_COL ETH1_MII_COL"),
[all …]
Dpinctrl-stm32mp257.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
10 #include "pinctrl-stm32.h"
29 STM32_FUNCTION(17, "ANALOG")
42 STM32_FUNCTION(12, "LCD_R3"),
46 STM32_FUNCTION(17, "ANALOG")
58 STM32_FUNCTION(12, "LCD_B0"),
62 STM32_FUNCTION(17, "ANALOG")
75 STM32_FUNCTION(12, "LCD_B1"),
79 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32f429.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH_MII_CRS"),
24 STM32_FUNCTION(17, "ANALOG")
33 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
35 STM32_FUNCTION(17, "ANALOG")
44 STM32_FUNCTION(12, "ETH_MDIO"),
46 STM32_FUNCTION(17, "ANALOG")
56 STM32_FUNCTION(12, "ETH_MII_COL"),
59 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32f746.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "pinctrl-stm32.h"
23 STM32_FUNCTION(12, "ETH_MII_CRS"),
25 STM32_FUNCTION(17, "ANALOG")
36 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
39 STM32_FUNCTION(17, "ANALOG")
49 STM32_FUNCTION(12, "ETH_MDIO"),
52 STM32_FUNCTION(17, "ANALOG")
62 STM32_FUNCTION(12, "ETH_MII_COL"),
65 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32f469.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
21 STM32_FUNCTION(12, "ETH_MII_CRS"),
23 STM32_FUNCTION(17, "ANALOG")
33 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
36 STM32_FUNCTION(17, "ANALOG")
45 STM32_FUNCTION(12, "ETH_MDIO"),
48 STM32_FUNCTION(17, "ANALOG")
59 STM32_FUNCTION(12, "ETH_MII_COL"),
62 STM32_FUNCTION(17, "ANALOG")
[all …]
/kernel/linux/linux-6.6/lib/zstd/compress/
Dclevels.h5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
17 /*-===== Pre-defined compression levels =====-*/
24 { /* "default" - for any srcSize > 256 KB */
26 { 19, 12, 13, 1, 6, 1, ZSTD_fast }, /* base for negative levels */
29 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
38 { 22, 22, 23, 6, 5, 32, ZSTD_lazy2 }, /* level 12 */
43 { 23, 23, 22, 5, 4, 64, ZSTD_btopt }, /* level 17 */
52 { 18, 12, 13, 1, 5, 1, ZSTD_fast }, /* base for negative levels */
56 { 18, 16, 17, 3, 5, 2, ZSTD_greedy }, /* level 4.*/
[all …]
/kernel/linux/linux-6.6/arch/arm64/crypto/
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
37 * The SHA-512 round constants
111 ld1 {v8.2d-v11.2d}, [x0]
115 ld1 {v20.2d-v23.2d}, [x3], #64
118 0: ld1 {v12.2d-v15.2d}, [x1], #64
119 ld1 {v16.2d-v19.2d}, [x1], #64
138 // v0 ab cd -- ef gh ab
139 // v1 cd -- ef gh ab cd
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
37 * The SHA-512 round constants
111 ld1 {v8.2d-v11.2d}, [x0]
115 ld1 {v20.2d-v23.2d}, [x3], #64
118 0: ld1 {v12.2d-v15.2d}, [x1], #64
119 ld1 {v16.2d-v19.2d}, [x1], #64
138 // v0 ab cd -- ef gh ab
139 // v1 cd -- ef gh ab cd
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/stm32/
Dpinctrl-stm32h743.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
24 STM32_FUNCTION(12, "ETH_MII_CRS"),
26 STM32_FUNCTION(17, "ANALOG")
39 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
42 STM32_FUNCTION(17, "ANALOG")
53 STM32_FUNCTION(12, "ETH_MDIO"),
57 STM32_FUNCTION(17, "ANALOG")
69 STM32_FUNCTION(12, "ETH_MII_COL"),
72 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32f769.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH_MII_CRS"),
24 STM32_FUNCTION(17, "ANALOG")
35 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
38 STM32_FUNCTION(17, "ANALOG")
48 STM32_FUNCTION(12, "ETH_MDIO"),
52 STM32_FUNCTION(17, "ANALOG")
63 STM32_FUNCTION(12, "ETH_MII_COL"),
66 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32mp157.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
10 #include "pinctrl-stm32.h"
25 STM32_FUNCTION(12, "ETH1_GMII_CRS ETH1_MII_CRS"),
27 STM32_FUNCTION(17, "ANALOG")
42 STM32_FUNCTION(12, "ETH1_GMII_RX_CLK ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
45 STM32_FUNCTION(17, "ANALOG")
58 STM32_FUNCTION(12, "ETH1_MDIO"),
62 STM32_FUNCTION(17, "ANALOG")
74 STM32_FUNCTION(12, "ETH1_GMII_COL ETH1_MII_COL"),
[all …]
Dpinctrl-stm32f746.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "pinctrl-stm32.h"
23 STM32_FUNCTION(12, "ETH_MII_CRS"),
25 STM32_FUNCTION(17, "ANALOG")
36 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
39 STM32_FUNCTION(17, "ANALOG")
49 STM32_FUNCTION(12, "ETH_MDIO"),
52 STM32_FUNCTION(17, "ANALOG")
62 STM32_FUNCTION(12, "ETH_MII_COL"),
65 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32f429.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH_MII_CRS"),
24 STM32_FUNCTION(17, "ANALOG")
33 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
35 STM32_FUNCTION(17, "ANALOG")
44 STM32_FUNCTION(12, "ETH_MDIO"),
46 STM32_FUNCTION(17, "ANALOG")
56 STM32_FUNCTION(12, "ETH_MII_COL"),
59 STM32_FUNCTION(17, "ANALOG")
[all …]
Dpinctrl-stm32f469.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
21 STM32_FUNCTION(12, "ETH_MII_CRS"),
23 STM32_FUNCTION(17, "ANALOG")
33 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
36 STM32_FUNCTION(17, "ANALOG")
45 STM32_FUNCTION(12, "ETH_MDIO"),
48 STM32_FUNCTION(17, "ANALOG")
59 STM32_FUNCTION(12, "ETH_MII_COL"),
62 STM32_FUNCTION(17, "ANALOG")
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
24 /* from BPP 4 to 12 in steps of 0.5 */
25 #define RC_RANGE_QP420_8BPC_MAX_NUM_BPP 17
70 { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
93 { 12, 11, 11, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 5,
95 { 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6,
97 { 12, 12, 12, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7,
99 { 12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7,
101 { 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8,
103 { 15, 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 9,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_vdsc.c1 // SPDX-License-Identifier: MIT
57 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
58 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
59 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
60 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
64 { 768, 15, 6144, 7, 17, 15, 15, {
65 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
66 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
67 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
68 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
[all …]
/kernel/linux/linux-6.6/include/dt-bindings/memory/
Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22 * modules dma-address-region larbs-ports
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
110 #define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
137 #define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
156 #define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
161 #define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
186 #define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16))
[all …]

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