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/kernel/linux/linux-5.10/drivers/gpu/drm/exynos/
Dregs-scaler.h206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
231 #define SCALER_SRC_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
243 #define SCALER_SRC_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/exynos/
Dregs-scaler.h206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
231 #define SCALER_SRC_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
243 #define SCALER_SRC_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
[all …]
/kernel/linux/linux-6.6/arch/arm64/crypto/
Dsha512-ce-core.S85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
101 sha512h2 q\i3, q\i1, v\i0\().2d
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Dsha512-ce-core.S85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
101 sha512h2 q\i3, q\i1, v\i0\().2d
[all …]
/kernel/linux/linux-6.6/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
/kernel/linux/linux-6.6/sound/soc/qcom/
Dlpass-sc7280.c113 struct lpass_variant *v = drvdata->variant; in sc7280_lpass_alloc_dma_channel() local
120 v->rdma_channels); in sc7280_lpass_alloc_dma_channel()
122 if (chan >= v->rdma_channels) in sc7280_lpass_alloc_dma_channel()
126 v->wrdma_channel_start + in sc7280_lpass_alloc_dma_channel()
127 v->wrdma_channels, in sc7280_lpass_alloc_dma_channel()
128 v->wrdma_channel_start); in sc7280_lpass_alloc_dma_channel()
130 if (chan >= v->wrdma_channel_start + v->wrdma_channels) in sc7280_lpass_alloc_dma_channel()
137 v->hdmi_rdma_channels); in sc7280_lpass_alloc_dma_channel()
138 if (chan >= v->hdmi_rdma_channels) in sc7280_lpass_alloc_dma_channel()
144 v->rxtx_rdma_channels); in sc7280_lpass_alloc_dma_channel()
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
/kernel/linux/linux-6.6/drivers/i3c/master/mipi-i3c-hci/
Dcmd_v1.c27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) argument
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) argument
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) argument
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) argument
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) argument
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) argument
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) argument
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v) argument
42 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v) argument
45 #define CMD_I0_RNW W0_BIT_(29)
[all …]
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_micfil.h42 #define MICFIL_CTRL1_PDMIEN_SHIFT 29
58 #define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \ argument
84 #define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \ argument
90 #define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \ argument
100 #define MICFIL_STAT_LOWFREQF_SHIFT 29
103 #define MICFIL_STAT_CHXF_SHIFT(v) (v) argument
104 #define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) argument
105 #define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) argument
112 #define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \ argument
116 #define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v) argument
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/verisilicon/
Dhantro_g1_regs.h136 #define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29)
144 #define G1_REG_DEC_CTRL4_BITPLANE2_E BIT(29)
173 #define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29)
313 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
314 #define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16)) argument
315 #define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0) argument
316 #define G1_REG_PP_DATA_DISC_E(v) ((v) ? BIT(9) : 0) argument
317 #define G1_REG_PP_CLK_GATE_E(v) ((v) ? BIT(8) : 0) argument
318 #define G1_REG_PP_IN_ENDIAN(v) ((v) ? BIT(7) : 0) argument
319 #define G1_REG_PP_OUT_ENDIAN(v) ((v) ? BIT(6) : 0) argument
[all …]
Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/hantro/
Dhantro_g1_regs.h134 #define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29)
142 #define G1_REG_DEC_CTRL4_BITPLANE2_E BIT(29)
171 #define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29)
311 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
312 #define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16)) argument
313 #define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0) argument
314 #define G1_REG_PP_DATA_DISC_E(v) ((v) ? BIT(9) : 0) argument
315 #define G1_REG_PP_CLK_GATE_E(v) ((v) ? BIT(8) : 0) argument
316 #define G1_REG_PP_IN_ENDIAN(v) ((v) ? BIT(7) : 0) argument
317 #define G1_REG_PP_OUT_ENDIAN(v) ((v) ? BIT(6) : 0) argument
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/sunxi/sun6i-mipi-csi2/
Dsun6i_mipi_csi2_reg.h17 #define SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(v) ((((v) - 1) << 8) & \ argument
19 #define SUN6I_MIPI_CSI2_CFG_LANE_COUNT(v) (((v) - 1) & GENMASK(1, 0)) argument
32 #define SUN6I_MIPI_CSI2_CH_INT_EN_EOT_ERR BIT(29)
49 #define SUN6I_MIPI_CSI2_CH_INT_PD_EOT_ERR BIT(29)
/kernel/linux/linux-6.6/arch/alpha/kernel/
Dentry.S47 * regs 29-30 saved and set up by PAL-code
314 .cfi_rel_offset $29, 29*8
373 .cfi_restore $29
691 #define V(n) stt $f##n, FR(n) macro
692 V( 0); V( 1); V( 2); V( 3)
693 V( 4); V( 5); V( 6); V( 7)
694 V( 8); V( 9); V(10); V(11)
695 V(12); V(13); V(14); V(15)
696 V(16); V(17); V(18); V(19)
697 V(20); V(21); V(22); V(23)
[all …]
/kernel/linux/linux-5.10/include/linux/spi/
Dmxs-spi.h20 #define BM_SSP_CTRL0_RUN (1 << 29)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ argument
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \ argument
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
67 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \ argument
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
93 #define BF_SSP_CTRL1_SSP_MODE(v) \ argument
94 (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
/kernel/linux/linux-6.6/include/linux/spi/
Dmxs-spi.h20 #define BM_SSP_CTRL0_RUN (1 << 29)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ argument
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \ argument
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
67 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \ argument
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
93 #define BF_SSP_CTRL1_SSP_MODE(v) \ argument
94 (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
/kernel/linux/linux-6.6/drivers/platform/x86/intel/pmt/
Dcrashlog.c29 * Bits 29 and 30 control the state of bit 31.
31 * Bit 29 will clear bit 31, if set, allowing a new crashlog to be captured.
35 #define CRASHLOG_FLAG_TRIGGER_CLEAR BIT(29)
45 #define GET_ACCESS(v) ((v) & GENMASK(3, 0)) argument
46 #define GET_TYPE(v) (((v) & GENMASK(7, 4)) >> 4) argument
47 #define GET_VERSION(v) (((v) & GENMASK(19, 16)) >> 16) argument
49 #define GET_SIZE(v) ((v) * sizeof(u32)) argument
/kernel/linux/linux-6.6/drivers/video/fbdev/
Dvalkyriefb.h8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/
Dvalkyriefb.h8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
/kernel/linux/linux-6.6/drivers/scsi/pm8001/
Dpm80xx_hwi.h125 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
343 /* Bits [30:29] - Reserved */
366 u32 reserved[29];
467 u32 reserved[29];
488 u32 reserved1[29];
693 u32 reserved[29];
755 __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
819 __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
970 __le32 reserved[29];
980 __le32 profile[29];
[all …]
/kernel/linux/linux-5.10/drivers/scsi/pm8001/
Dpm80xx_hwi.h125 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
343 /* Bits [30:29] - Reserved */
366 u32 reserved[29];
467 u32 reserved[29];
488 u32 reserved1[29];
698 u32 reserved[29];
760 __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
824 __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
975 u32 reserved[29];
985 __le32 profile[29];
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/nxp/dw100/
Ddw100_regs.h37 #define DW100_MAP_LUT_ADDR_ADDR(addr) (((addr) >> 4) & GENMASK(29, 0))
42 #define DW100_IMG_Y_BASE(base) (((base) >> 4) & GENMASK(29, 0))
44 #define DW100_IMG_UV_BASE(base) (((base) >> 4) & GENMASK(29, 0))
86 #define DW100_BOUNDARY_PIXEL_V(v) (((v) & GENMASK(7, 0)) << 0) argument
111 #define DW100_DST_IMG_Y_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0))
112 #define DW100_DST_IMG_UV_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0))
/kernel/linux/linux-6.6/drivers/media/v4l2-core/
Dv4l2-vp9.c18 { 92, 45, 102, 136, 116, 180, 74, 90, 100 }, /*left = v */
27 }, { /* above = v */
29 { 43, 46, 168, 134, 107, 128, 69, 142, 92 }, /*left = v */
30 { 44, 29, 68, 159, 201, 177, 50, 57, 77 }, /*left = h */
40 { 55, 44, 68, 166, 179, 192, 57, 57, 108 }, /*left = v */
51 { 59, 38, 83, 112, 103, 162, 98, 136, 90 }, /*left = v */
53 { 67, 30, 29, 84, 86, 191, 102, 91, 59 }, /*left = d45 */
57 { 77, 19, 29, 112, 142, 228, 55, 66, 36 }, /*left = d207*/
58 { 61, 29, 29, 93, 97, 165, 83, 175, 162 }, /*left = d63 */
61 { 69, 23, 29, 128, 83, 199, 46, 44, 101 }, /*left = dc */
[all …]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Dsonypi.h38 #define SONYPI_EVENT_FNKEY_S 29
83 #define SONYPI_IOCGBRT _IOR('v', 0, __u8)
84 #define SONYPI_IOCSBRT _IOW('v', 0, __u8)
85 #define SONYPI_IOCGBAT1CAP _IOR('v', 2, __u16)
86 #define SONYPI_IOCGBAT1REM _IOR('v', 3, __u16)
87 #define SONYPI_IOCGBAT2CAP _IOR('v', 4, __u16)
88 #define SONYPI_IOCGBAT2REM _IOR('v', 5, __u16)
92 #define SONYPI_IOCGBATFLAGS _IOR('v', 7, __u8)
93 #define SONYPI_IOCGBLUE _IOR('v', 8, __u8)
94 #define SONYPI_IOCSBLUE _IOW('v', 9, __u8)
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
Dsun8i_a83t_dphy.h34 #define SUN8I_A83T_DPHY_ANA0_RINT(v) (((v) << 28) & GENMASK(29, 28)) argument
35 #define SUN8I_A83T_DPHY_ANA0_SNK(v) (((v) << 20) & GENMASK(22, 20)) argument

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