Searched +full:32 +full:e2d000 (Results 1 – 4 of 4) sorted by relevance
60 should be multiple of 32 input interrupts and up to 512 interrupts.80 interrupt-controller@32e2d000 {
61 should be multiple of 32 input interrupts and up to 512 interrupts.81 interrupt-controller@32e2d000 {
407 gpio-ranges = <&iomuxc 0 87 32>;799 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;1099 bus@32c00000 { /* AIPS4 */1106 irqsteer: interrupt-controller@32e2d000 {
637 gpio-ranges = <&iomuxc 0 87 32>;1106 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;1591 aips4: bus@32c00000 { /* AIPS4 */1598 irqsteer: interrupt-controller@32e2d000 {