Searched full:515 (Results 1 – 25 of 119) sorted by relevance
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22 #define BRK_KPROBE_BP 515 /* Kprobe break */
32 #define SDX65_SLAVE_AUDIO 515
45 #define QDU1000_SLAVE_AHB2PHY_EAST 515
78 #define SM8450_SLAVE_AOSS 515
89 #define SC8280XP_SLAVE_AHB2PHY_1 515
28 #define BRK_KPROBE_BP 515 /* Kprobe break */
17 #define ENOIOCTLCMD 515 /* No ioctl command */
64 515: fpga3 out reset
30 #define BRK_KPROBE_BP 515
102 clocks = <&cpg CPG_MOD 515>;150 clocks = <&cpg CPG_MOD 515>;
181 clocks = <&cpg CPG_MOD 515>;187 resets = <&cpg 515>;
35 1-255: 515us + val * 35us (up to 9.440ms)
159 * 515 for the 2-way. That appears to be overkill, so for now, in create_cpu_loop()160 * impose a minimum of 750 or 515. in create_cpu_loop()162 fmin = (nr_cores > 2) ? 750 : 515; in create_cpu_loop()
161 * 515 for the 2-way. That appears to be overkill, so for now, in create_cpu_loop()162 * impose a minimum of 750 or 515. in create_cpu_loop()164 fmin = (nr_cores > 2) ? 750 : 515; in create_cpu_loop()
119 * DMAx hardware registers (p.515 in 440SPe UM 1.22)
122 * DMAx hardware registers (p.515 in 440SPe UM 1.22)
193 #define CLK_SCLK_ISP_SENSOR1 515
33 #define NIWD_MAX_TIMEOUT 515