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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
22 * Adjustable tx de-emphasis (FFE)
31 The SERDES6G is a high-speed SERDES interface, which can operate at
34 * 100 Mbps (100BASE-FX)
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
[all …]
Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
23 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
36 #define MDIO_DEVS1 5 /* Devices in package */
49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
57 /* Media-dependent registers. */
58 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
59 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
60 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
[all …]
/kernel/linux/linux-6.6/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
23 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
36 #define MDIO_DEVS1 5 /* Devices in package */
49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
[all …]
/kernel/linux/linux-6.6/Documentation/networking/
Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
208 Now just make sure that phydev->supported and phydev->advertising have any
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/lan966x/
Dlan966x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
52 #define PGID_CPU (PGID_AGGR - 6)
53 #define PGID_UC (PGID_AGGR - 5)
54 #define PGID_BC (PGID_AGGR - 4)
55 #define PGID_MC (PGID_AGGR - 3)
56 #define PGID_MCIPV4 (PGID_AGGR - 2)
57 #define PGID_MCIPV6 (PGID_AGGR - 1)
59 /* Non-reserved PGIDs, used for general purpose */
79 #define FDMA_DCB_INFO_DATAL(x) ((x) & GENMASK(15, 0)) argument
81 #define FDMA_DCB_STATUS_BLOCKL(x) ((x) & GENMASK(15, 0)) argument
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb3/
Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
93 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
94 rv->reg_addr, rv->clear_bits, in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb3/
Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
93 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
94 rv->reg_addr, rv->clear_bits, in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/
Dserdes.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 /* 10GBASE-R and 10GBASE-X4/X2 */
61 /* 1000BASE-X and SGMII */
107 #define MV88E6393X_SERDES_POC_PDOWN BIT(5)
146 /* Return the (first) SERDES lane address a port is using, -errno otherwise. */
150 if (!chip->info->ops->serdes_get_lane) in mv88e6xxx_serdes_get_lane()
151 return -EOPNOTSUPP; in mv88e6xxx_serdes_get_lane()
153 return chip->info->ops->serdes_get_lane(chip, port); in mv88e6xxx_serdes_get_lane()
159 if (!chip->info->ops->serdes_irq_mapping) in mv88e6xxx_serdes_irq_mapping()
162 return chip->info->ops->serdes_irq_mapping(chip, port); in mv88e6xxx_serdes_irq_mapping()
Dserdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
45 state->link = false; in mv88e6xxx_pcs_decode_state()
53 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_pcs_decode_state()
54 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); in mv88e6xxx_pcs_decode_state()
61 state->duplex = status & in mv88e6xxx_pcs_decode_state()
66 state->pause |= MLO_PAUSE_TX; in mv88e6xxx_pcs_decode_state()
68 state->pause |= MLO_PAUSE_RX; in mv88e6xxx_pcs_decode_state()
72 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) in mv88e6xxx_pcs_decode_state()
73 state->speed = SPEED_2500; in mv88e6xxx_pcs_decode_state()
75 state->speed = SPEED_1000; in mv88e6xxx_pcs_decode_state()
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
72 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
76 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
77 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
126 if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310) in mv10g_hwmon_read_temp_reg()
[all …]
Dbcm84881.c1 // SPDX-License-Identifier: GPL-2.0
2 // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
5 // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
6 // interface according to the operating speed between 10GBASE-R,
7 // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
34 switch (phydev->interface) { in bcm84881_config_init()
40 return -ENODEV; in bcm84881_config_init()
50 if (!phydev->is_c45 || in bcm84881_probe()
51 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in bcm84881_probe()
52 return -ENODEV; in bcm84881_probe()
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/
Dserdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
57 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_serdes_pcs_get_state()
58 state->duplex = status & in mv88e6xxx_serdes_pcs_get_state()
63 state->pause |= MLO_PAUSE_TX; in mv88e6xxx_serdes_pcs_get_state()
65 state->pause |= MLO_PAUSE_RX; in mv88e6xxx_serdes_pcs_get_state()
69 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) in mv88e6xxx_serdes_pcs_get_state()
70 state->speed = SPEED_2500; in mv88e6xxx_serdes_pcs_get_state()
72 state->speed = SPEED_1000; in mv88e6xxx_serdes_pcs_get_state()
75 state->speed = SPEED_100; in mv88e6xxx_serdes_pcs_get_state()
78 state->speed = SPEED_10; in mv88e6xxx_serdes_pcs_get_state()
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
171 return phydev->drv->driver_data; in to_mv3310_chip()
[all …]
Dbcm84881.c1 // SPDX-License-Identifier: GPL-2.0
2 // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
5 // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
6 // interface according to the operating speed between 10GBASE-R,
7 // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
34 switch (phydev->interface) { in bcm84881_config_init()
40 return -ENODEV; in bcm84881_config_init()
50 if (!phydev->is_c45 || in bcm84881_probe()
51 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in bcm84881_probe()
52 return -ENODEV; in bcm84881_probe()
[all …]
/kernel/linux/linux-6.6/drivers/phy/microchip/
Dlan966x_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
21 gbase, ginst, gcnt, gwidth, \ argument
23 (gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth))
80 SERDES_MUX_QSGMII(SERDES6G(2), 5, HSIO_HW_CFG_QSGMII_ENA,
111 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
116 HSIO_HW_CFG_GMII_ENA_SET(BIT(5))),
187 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) | in lan966x_sd6g40_reg_cfg()
188 HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) | in lan966x_sd6g40_reg_cfg()
189 HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) | in lan966x_sd6g40_reg_cfg()
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-7040-mochabin.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-7040.dtsi"
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
34 sfp_eth0: sfp-eth0 {
36 i2c-bus = <&cp0_i2c1>;
37 los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
38 mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
[all …]
Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
/kernel/linux/linux-6.6/drivers/net/
Dmdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mdio.c: Generic support for MDIO-compatible transceivers
4 * Copyright 2006-2009 Solarflare Communications Inc.
14 MODULE_DESCRIPTION("Generic support for MDIO-compatible transceivers");
15 MODULE_AUTHOR("Copyright 2006-2009 Solarflare Communications Inc.");
19 * mdio45_probe - probe for an MDIO (clause 45) device
32 for (mmd = 1; mmd <= 5; mmd++) { in mdio45_probe()
34 stat2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_STAT2); in mdio45_probe()
40 devs1 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS1); in mdio45_probe()
41 devs2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS2); in mdio45_probe()
[all …]
/kernel/linux/linux-5.10/drivers/net/
Dmdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mdio.c: Generic support for MDIO-compatible transceivers
4 * Copyright 2006-2009 Solarflare Communications Inc.
14 MODULE_DESCRIPTION("Generic support for MDIO-compatible transceivers");
15 MODULE_AUTHOR("Copyright 2006-2009 Solarflare Communications Inc.");
19 * mdio45_probe - probe for an MDIO (clause 45) device
32 for (mmd = 1; mmd <= 5; mmd++) { in mdio45_probe()
34 stat2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_STAT2); in mdio45_probe()
40 devs1 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS1); in mdio45_probe()
41 devs2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS2); in mdio45_probe()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
34 v_3_3: regulator-3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "v_3_3";
[all …]
/kernel/linux/linux-6.6/include/linux/
Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
79 * Set phydev->irq to PHY_POLL if interrupts are not supported,
83 #define PHY_POLL -1
84 #define PHY_MAC_INTERRUPT -2
93 * enum phy_interface_t - Interface Mode definitions
95 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
97 * @PHY_INTERFACE_MODE_MII: Media-independent interface
98 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
99 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
[all …]
/kernel/linux/linux-6.6/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
32 #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5)
42 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5)
69 #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5)
71 #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5)
82 #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5)
108 /* Relative to priv->regmap */
[all …]

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