Searched full:bwadj (Results 1 – 6 of 6) sorted by relevance
68 BWADJ--->72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
23 /* clkr: 4bits, clkf1: 6bits, clkod: 4bits, bwadj: 4bits */
312 u32 bwadj; member410 reg |= FIELD_PREP(K210_PLL_BWADJ, pll_cfg->bwadj); in k210_pll_enable_hw()
1399 * BWADJ value