| /kernel/linux/linux-6.6/drivers/crypto/intel/qat/qat_common/ |
| D | icp_qat_hw_20_comp.h | 23 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr) in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER() argument
27 QAT_FIELD_SET(val32, csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
30 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
36 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
39 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
42 QAT_FIELD_SET(val32, csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
45 QAT_FIELD_SET(val32, csr.hash_col, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
48 QAT_FIELD_SET(val32, csr.hash_update, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
51 QAT_FIELD_SET(val32, csr.skip_ctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_csr.c | 33 * DOC: csr support for dmc
35 * Display Context Save and Restore (CSR) firmware support added from gen9
296 * CSR firmware is read from a .bin file and kept in internal memory one time.
302 u32 *payload = dev_priv->csr.dmc_payload; in intel_csr_load_program()
307 "No CSR support available for this platform\n"); in intel_csr_load_program()
311 if (!dev_priv->csr.dmc_payload) { in intel_csr_load_program()
313 "Tried to program CSR with empty payload\n"); in intel_csr_load_program()
317 fw_size = dev_priv->csr.dmc_fw_size; in intel_csr_load_program()
328 for (i = 0; i < dev_priv->csr.mmio_count; i++) { in intel_csr_load_program()
329 intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i], in intel_csr_load_program()
[all …]
|
| /kernel/linux/linux-6.6/arch/sparc/kernel/ |
| D | ebus.c | 74 u32 csr = 0; in ebus_dma_irq() local
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
99 u32 csr; in ebus_dma_register() local
113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
118 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
[all …]
|
| /kernel/linux/linux-5.10/arch/sparc/kernel/ |
| D | ebus.c | 74 u32 csr = 0; in ebus_dma_irq() local
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
99 u32 csr; in ebus_dma_register() local
113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
118 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
[all …]
|
| /kernel/linux/linux-6.6/arch/alpha/kernel/ |
| D | core_tsunami.c | 181 volatile unsigned long *csr; in tsunami_pci_tbi() local
186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
194 *csr = value; in tsunami_pci_tbi()
196 *csr; in tsunami_pci_tbi()
227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
251 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
[all …]
|
| D | core_wildfire.c | 121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
[all …]
|
| D | core_titan.c | 207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
[all …]
|
| /kernel/linux/linux-5.10/arch/alpha/kernel/ |
| D | core_tsunami.c | 181 volatile unsigned long *csr; in tsunami_pci_tbi() local
186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
194 *csr = value; in tsunami_pci_tbi()
196 *csr; in tsunami_pci_tbi()
227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
251 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
[all …]
|
| D | core_wildfire.c | 121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
[all …]
|
| D | core_titan.c | 207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
[all …]
|
| /kernel/linux/linux-6.6/drivers/crypto/starfive/ |
| D | jh7110-rsa.c | 100 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
102 writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET); in starfive_rsa_montgomery_form()
108 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
109 rctx->csr.pka.cln_done = 1; in starfive_rsa_montgomery_form()
110 rctx->csr.pka.opsize = opsize; in starfive_rsa_montgomery_form()
111 rctx->csr.pka.exposize = opsize; in starfive_rsa_montgomery_form()
112 rctx->csr.pka.cmd = CRYPTO_CMD_PRE; in starfive_rsa_montgomery_form()
113 rctx->csr.pka.start = 1; in starfive_rsa_montgomery_form()
114 rctx->csr.pka.not_r2 = 1; in starfive_rsa_montgomery_form()
115 rctx->csr.pka.ie = 1; in starfive_rsa_montgomery_form()
[all …]
|
| /kernel/linux/linux-5.10/drivers/usb/musb/ |
| D | musb_gadget.c | 229 u16 fifo_count = 0, csr; in txstate() local
248 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
254 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
256 musb_ep->end_point.name, csr); in txstate()
260 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
262 musb_ep->end_point.name, csr); in txstate()
268 csr); in txstate()
275 /* setup DMA, then program endpoint CSR */ in txstate()
301 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
303 musb_writew(epio, MUSB_TXCSR, csr in txstate()
[all …]
|
| D | musb_gadget_ep0.c | 243 u16 csr; in service_zero_data_request() local
266 csr = musb_readw(regs, MUSB_TXCSR); in service_zero_data_request()
267 csr |= MUSB_TXCSR_CLRDATATOG | in service_zero_data_request()
269 csr &= ~(MUSB_TXCSR_P_SENDSTALL | in service_zero_data_request()
272 musb_writew(regs, MUSB_TXCSR, csr); in service_zero_data_request()
274 csr = musb_readw(regs, MUSB_RXCSR); in service_zero_data_request()
275 csr |= MUSB_RXCSR_CLRDATATOG | in service_zero_data_request()
277 csr &= ~(MUSB_RXCSR_P_SENDSTALL | in service_zero_data_request()
279 musb_writew(regs, MUSB_RXCSR, csr); in service_zero_data_request()
403 u16 csr; in service_zero_data_request() local
[all …]
|
| /kernel/linux/linux-6.6/drivers/usb/musb/ |
| D | musb_gadget.c | 229 u16 fifo_count = 0, csr; in txstate() local
248 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
254 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
256 musb_ep->end_point.name, csr); in txstate()
260 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
262 musb_ep->end_point.name, csr); in txstate()
268 csr); in txstate()
275 /* setup DMA, then program endpoint CSR */ in txstate()
301 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
303 musb_writew(epio, MUSB_TXCSR, csr in txstate()
[all …]
|
| D | musb_gadget_ep0.c | 243 u16 csr; in service_zero_data_request() local
266 csr = musb_readw(regs, MUSB_TXCSR); in service_zero_data_request()
267 csr |= MUSB_TXCSR_CLRDATATOG | in service_zero_data_request()
269 csr &= ~(MUSB_TXCSR_P_SENDSTALL | in service_zero_data_request()
272 musb_writew(regs, MUSB_TXCSR, csr); in service_zero_data_request()
274 csr = musb_readw(regs, MUSB_RXCSR); in service_zero_data_request()
275 csr |= MUSB_RXCSR_CLRDATATOG | in service_zero_data_request()
277 csr &= ~(MUSB_RXCSR_P_SENDSTALL | in service_zero_data_request()
279 musb_writew(regs, MUSB_RXCSR, csr); in service_zero_data_request()
403 u16 csr; in service_zero_data_request() local
[all …]
|
| /kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/ |
| D | icp_qat_hal.h | 90 #define SET_CAP_CSR(handle, csr, val) \ argument
91 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
92 #define GET_CAP_CSR(handle, csr) \ argument
93 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
94 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val) argument
95 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr) argument
99 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr)) argument
100 #define SET_AE_CSR(handle, ae, csr, val) \ argument
101 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
102 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
|
| /kernel/linux/linux-5.10/arch/arm/mach-prima2/ |
| D | Kconfig | 3 bool "CSR SiRF"
14 Support for CSR SiRFprimaII/Marco/Polo platforms
18 comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
21 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
25 Support for CSR SiRFSoC ARM Cortex A9 Platform
28 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
34 Support for CSR SiRFSoC ARM Cortex A7 Platform
37 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
43 Support for CSR SiRFSoC ARM Cortex A9 Platform
|
| /kernel/linux/linux-6.6/drivers/scsi/ |
| D | sun3_scsi.c | 73 unsigned short csr; /* control/status reg */ member
117 /* bits in csr reg */
190 // safe bits for the CSR
196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
200 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr()
203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
204 if (csr & CSR_DMA_BUSERR) in scsi_sun3_intr()
206 if (csr & CSR_DMA_CONFLICT) in scsi_sun3_intr()
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr()
242 dregs->csr &= ~CSR_FIFO; in sun3scsi_dma_setup()
[all …]
|
| /kernel/linux/linux-5.10/drivers/scsi/ |
| D | sun3_scsi.c | 73 unsigned short csr; /* control/status reg */ member
117 /* bits in csr reg */
190 // safe bits for the CSR
196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
200 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr()
203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
204 if (csr & CSR_DMA_BUSERR) in scsi_sun3_intr()
206 if (csr & CSR_DMA_CONFLICT) in scsi_sun3_intr()
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr()
242 dregs->csr &= ~CSR_FIFO; in sun3scsi_dma_setup()
[all …]
|
| /kernel/linux/linux-6.6/arch/sh/kernel/cpu/ |
| D | adc.c | 16 unsigned char csr; in adc_single() local
22 csr = __raw_readb(ADCSR); in adc_single()
23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
24 __raw_writeb(csr, ADCSR); in adc_single()
27 csr = __raw_readb(ADCSR); in adc_single()
28 } while ((csr & ADCSR_ADF) == 0); in adc_single()
30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()
|
| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/ |
| D | adc.c | 16 unsigned char csr; in adc_single() local
22 csr = __raw_readb(ADCSR); in adc_single()
23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
24 __raw_writeb(csr, ADCSR); in adc_single()
27 csr = __raw_readb(ADCSR); in adc_single()
28 } while ((csr & ADCSR_ADF) == 0); in adc_single()
30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()
|
| /kernel/linux/linux-6.6/drivers/usb/gadget/udc/ |
| D | at91_udc.c | 111 u32 csr; in proc_ep_show() local
118 csr = __raw_readl(ep->creg); in proc_ep_show()
131 seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", in proc_ep_show()
132 csr, in proc_ep_show()
133 (csr & 0x07ff0000) >> 16, in proc_ep_show()
134 (csr & (1 << 15)) ? "enabled" : "disabled", in proc_ep_show()
135 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
136 types[(csr & 0x700) >> 8], in proc_ep_show()
139 (!(csr & 0x700)) in proc_ep_show()
140 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
[all …]
|
| /kernel/linux/linux-5.10/arch/riscv/include/asm/ |
| D | csr.h | 82 /* symbolic CSR names: */
157 #define csr_swap(csr, val) \ argument
160 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
166 #define csr_read(csr) \ argument
169 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
175 #define csr_write(csr, val) \ argument
178 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
183 #define csr_read_set(csr, val) \ argument
186 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
192 #define csr_set(csr, val) \ argument
[all …]
|
| /kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/ |
| D | core_feature_base.h | 47 /** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */
100 rv_csr_t d; /*!< Type used for csr data access */
141 rv_csr_t d; /*!< Type used for csr data access */
156 rv_csr_t d; /*!< Type used for csr data access */
178 rv_csr_t d; /*!< Type used for csr data access */
195 rv_csr_t d; /*!< Type used for csr data access */
212 rv_csr_t d; /*!< Type used for csr data access */
232 rv_csr_t d; /*!< Type used for csr data access */
255 rv_csr_t w; /*!< Type used for csr data access */
261 * \defgroup NMSIS_Core_CSR_Register_Access Core CSR Register Access
[all …]
|
| /kernel/linux/linux-6.6/arch/riscv/kvm/ |
| D | vcpu.c | 20 #include <asm/csr.h>
47 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_reset_vcpu() local
65 memcpy(csr, reset_csr, sizeof(*csr)); in kvm_riscv_reset_vcpu()
322 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_flush_interrupts() local
329 csr->hvip &= ~mask; in kvm_riscv_vcpu_flush_interrupts()
330 csr->hvip |= val; in kvm_riscv_vcpu_flush_interrupts()
341 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_sync_interrupts() local
344 csr->vsie = csr_read(CSR_VSIE); in kvm_riscv_vcpu_sync_interrupts()
348 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { in kvm_riscv_vcpu_sync_interrupts()
498 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_arch_vcpu_load() local
[all …]
|