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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
35 /* DSI D-PHY Layer Registers */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
42 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
50 /* DSI PPI Layer Registers */
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Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
83 * The DSI host controller needs this reset sequence according to NWL:
84 * 1. Deassert pclk reset to get access to DSI regs
85 * 2. Configure DSI Host and DPHY and enable DPHY
87 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
89 * DSI data
91 * TODO: Since panel_bridges do their DSI setup in enable we
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Dcdns-dsi.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/phy/phy-mipi-dphy.h>
71 #define DATA_LANE_EN(x) BIT((x) - 1)
488 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
490 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
502 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
507 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
512 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
519 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in cdns_dsi_mode2cfg()
522 bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format); in cdns_dsi_mode2cfg()
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Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
42 /* DSI layer registers */
43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
126 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
129 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
136 /* Lane enable PPI and DSI register bits */
164 int ret = ctx->error; in tc358764_clear_error()
166 ctx->error = 0; in tc358764_clear_error()
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/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
42 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
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Dlontium-lt9211.c1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
47 struct mipi_dsi_device *dsi; member
106 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, in lt9211_attach()
107 &ctx->bridge, flags); in lt9211_attach()
116 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3); in lt9211_read_chipid()
118 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret); in lt9211_read_chipid()
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Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
15 #include <linux/media-bus-format.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
83 * DSI data
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Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
38 /* DSI layer registers */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
121 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
122 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
125 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
132 /* Lane enable PPI and DSI register bits */
160 int ret = ctx->error; in tc358764_clear_error()
162 ctx->error = 0; in tc358764_clear_error()
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/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dmdfld_dsi_pkg_sender.c48 "RX SOT Error",
49 "RX SOT Sync Error",
50 "RX EOT Sync Error",
51 "RX Escape Mode Entry Error",
52 "RX LP TX Sync Error",
53 "RX HS Receive Timeout Error",
54 "RX False Control Error",
55 "RX ECC Single Bit Error",
56 "RX ECC Multibit Error",
57 "RX Checksum Error",
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dvlv_dsi_pll.c36 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
37 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
38 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
39 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
42 /* Get DSI clock from pixel clock */
49 /* DSI data rate = pixel clock * bits per pixel / lane count in dsi_clk_from_pclk()
67 drm_err(&dev_priv->drm, "DSI CLK Out of Range\n"); in dsi_calc_mnp()
68 return -ECHRNG; in dsi_calc_mnp()
85 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); in dsi_calc_mnp()
91 * +/- the required clock in dsi_calc_mnp()
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dvlv_dsi_pll.c40 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
41 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
42 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
43 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
46 /* Get DSI clock from pixel clock */
53 /* DSI data rate = pixel clock * bits per pixel / lane count in dsi_clk_from_pclk()
71 drm_err(&dev_priv->drm, "DSI CLK Out of Range\n"); in dsi_calc_mnp()
72 return -ECHRNG; in dsi_calc_mnp()
89 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); in dsi_calc_mnp()
95 * +/- the required clock in dsi_calc_mnp()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dchipone,icn6211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
10 - Jagan Teki <jagan@amarulasolutions.com>
13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
15 It has a flexible configuration of MIPI DSI signal input and
21 - chipone,icn6211
25 description: virtual channel number of a DSI peripheral
27 clock-names:
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Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358775 DSI to LVDS bridge
10 - Vinay Simha BN <simhavcs@gmail.com>
13 This binding supports DSI to LVDS bridge TC358775
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/mfd/dbx500-prcmu.h>
9 #include <dt-bindings/arm/ux500_pm_domains.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
37 #address-cells = <1>;
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/kernel/linux/linux-6.6/drivers/pinctrl/sunxi/
Dpinctrl-sun20i-d1.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
14 #include "pinctrl-sunxi.h"
36 SUNXI_FUNCTION(0x6, "uart0"), /* RX */
37 SUNXI_FUNCTION(0x7, "uart2"), /* RX */
38 SUNXI_FUNCTION(0x8, "ir"), /* RX */
59 SUNXI_FUNCTION(0x7, "uart4"), /* RX */
60 SUNXI_FUNCTION(0x8, "can0"), /* RX */
81 SUNXI_FUNCTION(0x7, "uart5"), /* RX */
82 SUNXI_FUNCTION(0x8, "can1"), /* RX */
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/kernel/linux/linux-6.6/arch/riscv/boot/dts/allwinner/
Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
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/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358775 DSI to LVDS bridge bindings
10 - Vinay Simha BN <simhavcs@gmail.com>
13 This binding supports DSI to LVDS bridge TC358775
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
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/kernel/linux/linux-6.6/drivers/gpu/drm/sprd/
Dsprd_dsi.c1 // SPDX-License-Identifier: GPL-2.0
139 return (readl(ctx->base + offset) & mask) >> shift; in dsi_reg_rd()
148 ret = readl(ctx->base + offset); in dsi_reg_wr()
151 writel(ret, ctx->base + offset); in dsi_reg_wr()
158 u32 ret = readl(ctx->base + offset); in dsi_reg_up()
160 writel((ret & ~mask) | (val & mask), ctx->base + offset); in dsi_reg_up()
165 struct sprd_dsi *dsi = context; in regmap_tst_io_write() local
166 struct dsi_context *ctx = &dsi->ctx; in regmap_tst_io_write()
169 return -EINVAL; in regmap_tst_io_write()
171 drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val); in regmap_tst_io_write()
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/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/cadence/
Dcdns-dsi-core.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/phy/phy-mipi-dphy.h>
25 #include "cdns-dsi-core.h"
27 #include "cdns-dsi-j721e.h"
72 #define DATA_LANE_EN(x) BIT((x) - 1)
448 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
450 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
462 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
467 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
472 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
Ddsi_host.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
27 #include "dsi.h"
28 #include "dsi.xml.h"
45 return -EINVAL; in dsi_get_version()
49 * makes all other registers 4-byte shifted down. in dsi_get_version()
53 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In in dsi_get_version()
60 /* older dsi host, there is no register shift */ in dsi_get_version()
68 return -EINVAL; in dsi_get_version()
84 return -EINVAL; in dsi_get_version()
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