| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | toshiba,tc358775.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
33 vddio-supply:
36 stby-gpios:
[all …]
|
| D | ti,sn65dsi83.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/dsa/b53/ |
| D | b53_serdes.c | 1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
37 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
39 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
42 WARN_ON(lane > 1); in b53_serdes_set_lane()
45 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
46 dev->serdes_lane = lane; in b53_serdes_set_lane()
49 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
52 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
56 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
59 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | toshiba,tc358775.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
34 vddio-supply:
38 stby-gpios:
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/dsa/b53/ |
| D | b53_serdes.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
[all …]
|
| /kernel/linux/linux-6.6/include/linux/phy/ |
| D | phy-lvds.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
16 * data lanes, starting from lane 0,
20 * phy to support dual link transmission,
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/connector/ |
| D | usb-connector.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
20 - enum:
21 - usb-a-connector
22 - usb-b-connector
23 - usb-c-connector
25 - items:
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/intel/ |
| D | phy-intel-lgm-combo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
20 #include <dt-bindings/phy/phy.h>
33 #define CR_ADDR(addr, lane) (((addr) + (lane) * 0x100) << 2) argument
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
114 return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid), in intel_cbphy_iphy_enable()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/ |
| D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
44 #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
[all …]
|
| D | tc358762.c | 1 // SPDX-License-Identifier: GPL-2.0
34 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
35 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
40 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
56 /* Lane enable PPI and DSI register bits */
73 int ret = ctx->error; in tc358762_clear_error()
75 ctx->error = 0; in tc358762_clear_error()
81 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write()
85 if (ctx->error) in tc358762_write()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/ |
| D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
[all …]
|
| D | tc358762.c | 1 // SPDX-License-Identifier: GPL-2.0
35 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
36 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
40 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
41 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
66 /* Lane enable PPI and DSI register bits */
84 int ret = ctx->error; in tc358762_clear_error()
86 ctx->error = 0; in tc358762_clear_error()
92 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write()
96 if (ctx->error) in tc358762_write()
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/intel/ |
| D | phy-intel-lgm-combo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
20 #include <dt-bindings/phy/phy.h>
33 #define CR_ADDR(addr, lane) (((addr) + (lane) * 0x100) << 2) argument
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
114 return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid), in intel_cbphy_iphy_enable()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/ |
| D | drm_of.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/media-bus-format.h>
25 * drm_of_crtc_port_mask - find the mask of a registered CRTC by port OF node
39 if (tmp->port == port) in drm_of_crtc_port_mask()
50 * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
83 * drm_of_component_match_add - Add a component helper OF node match rule
101 * drm_of_component_probe - Generic probe function for a component based master
121 if (!dev->of_node) in drm_of_component_probe()
122 return -EINVAL; in drm_of_component_probe()
129 port = of_parse_phandle(dev->of_node, "ports", i); in drm_of_component_probe()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-bus-usb | 10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
42 A devices's CDID, as 16 space-separated hex octets.
53 space-separated hex octets.
67 Contact: linux-usb@vger.kernel.org
101 What: /sys/bus/usb-serial/drivers/.../new_id
103 Contact: linux-usb@vger.kernel.org
106 extra bus folder "usb-serial" in sysfs; apart from that
131 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
147 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | icl_dsi.c | 71 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
83 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
108 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
115 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
116 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
117 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
118 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
121 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
126 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
[all …]
|
| D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation
43 * IOSF-SB port.
46 * houses a common lane part which contains the PLL and other common
47 * logic. CH0 common lane also contains the IOSF-SB logic for the
57 * each spline is made up of one Physical Access Coding Sub-Layer
62 * Additionally the PHY also contains an AUX lane with AUX blocks
68 * Generally on VLV/CHV the common lane corresponds to the pipe and
71 * For dual channel PHY (VLV/CHV):
100 * Dual channel PHY (VLV/CHV/BXT)
101 * ---------------------------------
[all …]
|
| /kernel/linux/linux-6.6/drivers/ufs/host/ |
| D | tc-dwc-g210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
15 #include "ufshcd-dwc.h"
16 #include "ufshci-dwc.h"
17 #include "tc-dwc-g210.h"
20 * tc_dwc_g210_setup_40bit_rmmi() - configure 40-bit RMMI.
23 * Return: 0 on success or non-zero value on failure.
83 * tc_dwc_g210_setup_20bit_rmmi_lane0() - configure 20-bit RMMI Lane 0.
86 * Return: 0 on success or non-zero value on failure.
135 * tc_dwc_g210_setup_20bit_rmmi_lane1() - configure 20-bit RMMI Lane 1.
[all …]
|
| /kernel/linux/linux-5.10/drivers/scsi/ufs/ |
| D | tc-dwc-g210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
13 #include "ufshcd-dwc.h"
14 #include "ufshci-dwc.h"
15 #include "tc-dwc-g210.h"
19 * This function configures Synopsys TC specific atributes (40-bit RMMI)
22 * Returns 0 on success or non-zero value on failure
83 * This function configures Synopsys TC 20-bit RMMI Lane 0
86 * Returns 0 on success or non-zero value on failure
136 * This function configures Synopsys TC 20-bit RMMI Lane 1
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation
39 * IOSF-SB port.
42 * houses a common lane part which contains the PLL and other common
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
53 * each spline is made up of one Physical Access Coding Sub-Layer
58 * Additionally the PHY also contains an AUX lane with AUX blocks
64 * Generally on VLV/CHV the common lane corresponds to the pipe and
67 * For dual channel PHY (VLV/CHV):
96 * Dual channel PHY (VLV/CHV/BXT)
97 * ---------------------------------
[all …]
|
| D | icl_dsi.c | 58 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
66 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
79 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
87 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
94 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
95 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
96 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
97 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
100 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
105 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | thunderbolt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
40 * enum tb_security_level - Thunderbolt security level
61 * struct tb - main thunderbolt bus structure
97 return (link - 1) / TB_LINKS_PER_PHY_PORT; in tb_phy_port_from_link()
101 * struct tb_property_dir - XDomain property directory
123 * struct tb_property - XDomain property
175 * enum tb_link_width - Thunderbolt/USB4 link width
176 * @TB_LINK_WIDTH_SINGLE: Single lane link
177 * @TB_LINK_WIDTH_DUAL: Dual lane symmetric link
178 * @TB_LINK_WIDTH_ASYM_TX: Dual lane asymmetric Gen 4 link with 3 trasmitters
[all …]
|