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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
32 Reflects the memory layout with four integer values per bank. Format:
33 <bank-number> 0 <parent address of bank> <size>
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
[all …]
Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@foss.st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
[all …]
Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
10 bank contains the MIX registers. The second bank the corresponding
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
10 bank contains the MIX registers. The second bank the corresponding
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/leds/
Dleds-lm36274.txt1 * Texas Instruments LM36274 4-Channel LCD Backlight Driver w/Integrated Bias
3 The LM36274 is an integrated four-channel WLED driver and LCD bias supply.
4 The backlight boost provides the power to bias four parallel LED strings with
5 up to 29V total output voltage. The 11-bit LED current is programmable via
9 Documentation/devicetree/bindings/mfd/ti-lmu.txt
12 Documentation/devicetree/bindings/regulator/lm363x-regulator.txt
15 - compatible:
16 "ti,lm36274-backlight"
17 - reg : 0
18 - #address-cells : 1
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/leds/
Dleds-lm36274.txt1 * Texas Instruments LM36274 4-Channel LCD Backlight Driver w/Integrated Bias
3 The LM36274 is an integrated four-channel WLED driver and LCD bias supply.
4 The backlight boost provides the power to bias four parallel LED strings with
5 up to 29V total output voltage. The 11-bit LED current is programmable via
9 Documentation/devicetree/bindings/mfd/ti-lmu.txt
12 Documentation/devicetree/bindings/regulator/lm363x-regulator.txt
15 - compatible:
16 "ti,lm36274-backlight"
17 - reg : 0
18 - #address-cells : 1
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/kernel/linux/linux-5.10/drivers/mtd/maps/
Dintel_vr_nor.c4 * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
7 * The Vermilion Range Expansion Bus supports four chip selects, each of which
9 * is a 256MiB memory region containing the address spaces for all four of the
62 #define TIMING_BYTE_EN (1 << 0) /* 8-bit vs 16-bit bus */
67 mtd_device_unregister(p->info); in vr_nor_destroy_partitions()
72 /* register the flash bank */ in vr_nor_init_partitions()
73 /* partition the flash bank */ in vr_nor_init_partitions()
74 return mtd_device_register(p->info, NULL, 0); in vr_nor_init_partitions()
79 map_destroy(p->info); in vr_nor_destroy_mtd_setup()
88 for (type = probe_types; !p->info && *type; type++) in vr_nor_mtd_setup()
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/kernel/linux/linux-6.6/drivers/mtd/maps/
Dintel_vr_nor.c4 * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
7 * The Vermilion Range Expansion Bus supports four chip selects, each of which
9 * is a 256MiB memory region containing the address spaces for all four of the
62 #define TIMING_BYTE_EN (1 << 0) /* 8-bit vs 16-bit bus */
67 mtd_device_unregister(p->info); in vr_nor_destroy_partitions()
72 /* register the flash bank */ in vr_nor_init_partitions()
73 /* partition the flash bank */ in vr_nor_init_partitions()
74 return mtd_device_register(p->info, NULL, 0); in vr_nor_init_partitions()
79 map_destroy(p->info); in vr_nor_destroy_mtd_setup()
88 for (type = probe_types; !p->info && *type; type++) in vr_nor_mtd_setup()
[all …]
Dnetsc520.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* netsc520.c -- MTD map driver for AMD NetSc520 Demonstration Board
5 * based on sc520cdp.c by Sysgo Real-Time Solutions GmbH
8 * from AMD. It has a single back of 16 megs of 32-bit Flash ROM and another
23 ** The single, 16 megabyte flash bank is divided into four virtual
34 ** not be touched - it is possible to corrupt the BIOS image by
70 .name = "netsc520 Flash Bank",
89 return -EIO; in init_netsc520()
102 return -ENXIO; in init_netsc520()
105 mymtd->owner = THIS_MODULE; in init_netsc520()
/kernel/linux/linux-6.6/arch/powerpc/platforms/85xx/
Dp1022_ds.c42 * Board-specific initialization of the DIU. This code should probably be
77 * Note that we need to byte-swap the value before it's written to the AD
133 * obtain the upper four bits, we need to scan the LAW table. The entry which
134 * maps to the localbus will contain the upper four bits.
140 * If we only have 32-bit addressing, then the BRx address *is* the in lbc_br_to_phys()
153 /* Extract the upper four bits */ in lbc_br_to_phys()
181 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); in p1022ds_set_monitor_port()
193 lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc"); in p1022ds_set_monitor_port()
205 law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law"); in p1022ds_set_monitor_port()
217 iprop = of_get_property(law_node, "fsl,num-laws", NULL); in p1022ds_set_monitor_port()
[all …]
/kernel/linux/linux-6.6/drivers/hwspinlock/
Domap_hwspinlock.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2010-2021 Texas Instruments Incorporated - https://www.ti.com
8 * Hari Kanigeri <h-kanigeri2@ti.com>
9 * Ohad Ben-Cohen <ohad@wizery.com>
10 * Suman Anna <s-anna@ti.com>
40 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_trylock()
48 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_unlock()
77 struct device_node *node = pdev->dev.of_node; in omap_hwspinlock_probe()
78 struct hwspinlock_device *bank; in omap_hwspinlock_probe() local
86 return -ENODEV; in omap_hwspinlock_probe()
[all …]
/kernel/linux/linux-5.10/drivers/hwspinlock/
Domap_hwspinlock.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
8 * Hari Kanigeri <h-kanigeri2@ti.com>
9 * Ohad Ben-Cohen <ohad@wizery.com>
39 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_trylock()
47 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_unlock()
76 struct device_node *node = pdev->dev.of_node; in omap_hwspinlock_probe()
77 struct hwspinlock_device *bank; in omap_hwspinlock_probe() local
85 return -ENODEV; in omap_hwspinlock_probe()
95 pm_runtime_enable(&pdev->dev); in omap_hwspinlock_probe()
[all …]
/kernel/linux/linux-6.6/drivers/thermal/mediatek/
Dauxadc_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
109 /* The number of sensing points per bank */
119 #define MT8173_TEMP_MIN -20000
198 /* The number of sensing points per bank */
219 /* The number of sensing points per bank */
258 /* The number of sensing points per bank */
276 /* The number of sensing points per bank */
472 * The MT8173 thermal controller has four banks. Each bank can read up to
473 * four temperature sensors simultaneously. The MT8173 has a total of 5
[all …]
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * Total register block size is 0x1C for one bank of four ports (A, B, C, D).
14 * An optional second bank, with ports E, F, G, and H, may be present, starting
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
45 * @base: Base address of the register block for a GPIO bank
49 * @bank_read: Read a bank setting as a single 32-bit value
50 * @bank_write: Write a bank setting as a single 32-bit value
53 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55 * a value from (to) these registers. The IMR register consists of four 16-bit
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/85xx/
Dp1022_ds.c41 * Board-specific initialization of the DIU. This code should probably be
76 * Note that we need to byte-swap the value before it's written to the AD
132 * obtain the upper four bits, we need to scan the LAW table. The entry which
133 * maps to the localbus will contain the upper four bits.
139 * If we only have 32-bit addressing, then the BRx address *is* the in lbc_br_to_phys()
152 /* Extract the upper four bits */ in lbc_br_to_phys()
180 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); in p1022ds_set_monitor_port()
192 lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc"); in p1022ds_set_monitor_port()
204 law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law"); in p1022ds_set_monitor_port()
216 iprop = of_get_property(law_node, "fsl,num-laws", NULL); in p1022ds_set_monitor_port()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap-zoom-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "omap-gpmc-smsc911x.dtsi"
13 * Four port TL16CP754C serial port on GPMC,
20 bank-width = <2>;
21 reg-shift = <1>;
22 reg-io-width = <1>;
23 interrupt-parent = <&gpio4>;
25 clock-frequency = <1843200>;
26 current-speed = <115200>;
27 gpmc,mux-add-data = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap-zoom-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "omap-gpmc-smsc911x.dtsi"
13 * Four port TL16CP754C serial port on GPMC,
20 bank-width = <2>;
21 reg-shift = <1>;
22 reg-io-width = <1>;
23 interrupt-parent = <&gpio4>;
25 clock-frequency = <1843200>;
26 current-speed = <115200>;
27 gpmc,mux-add-data = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/thermal/
Dmtk_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
107 /* The number of sensing points per bank */
177 /* The number of sensing points per bank */
198 /* The number of sensing points per bank */
237 /* The number of sensing points per bank */
388 * The MT8173 thermal controller has four banks. Each bank can read up to
389 * four temperature sensors simultaneously. The MT8173 has a total of 5
390 * temperature sensors. We use each bank to measure a certain area of the
395 * the bank concept wouldn't be necessary here. However, the SVS (Smart
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
[all …]
Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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/kernel/linux/linux-6.6/Documentation/admin-guide/perf/
Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
12 Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
24 four groups:
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