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/kernel/linux/linux-6.6/arch/sparc/include/uapi/asm/
Dasi.h142 /* SpitFire and later extended ASIs. The "(III)" marker designates
143 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
168 #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
169 #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
170 #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
171 #define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
172 #define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
173 #define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
174 #define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
175 #define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
[all …]
/kernel/linux/linux-5.10/arch/sparc/include/uapi/asm/
Dasi.h142 /* SpitFire and later extended ASIs. The "(III)" marker designates
143 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
168 #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
169 #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
170 #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
171 #define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
172 #define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
173 #define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
174 #define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
175 #define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
[all …]
/kernel/linux/linux-6.6/arch/sparc/include/asm/
Ddcr.h5 /* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
6 #define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */
11 #define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */
Dchmctrl.h8 #define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
12 #define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
74 /* Memory Timing Control III */
/kernel/linux/linux-5.10/arch/sparc/include/asm/
Ddcr.h5 /* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
6 #define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */
11 #define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */
Dchmctrl.h8 #define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
12 #define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
74 /* Memory Timing Control III */
/kernel/linux/linux-6.6/drivers/media/rc/keymaps/
Drc-reddo.c3 * MSI DIGIVOX mini III remote controller keytable
12 * Derived from MSI DIGIVOX mini III remote (rc-msi-digivox-iii.c)
17 * MSI DIGIVOX mini III "Source" = KEY_VIDEO
/kernel/linux/linux-5.10/drivers/media/rc/keymaps/
Drc-reddo.c3 * MSI DIGIVOX mini III remote controller keytable
12 * Derived from MSI DIGIVOX mini III remote (rc-msi-digivox-iii.c)
17 * MSI DIGIVOX mini III "Source" = KEY_VIDEO
/kernel/linux/linux-6.6/Documentation/driver-api/
Dzorro.rst15 There are two types of Zorro buses, Zorro II and Zorro III:
20 - Zorro III is a 32-bit extension of Zorro II, which is backwards compatible
21 with Zorro II. The Zorro III address space lies outside the first 16 MB.
87 - Zorro III address space must be mapped explicitly using z_ioremap() first
/kernel/linux/linux-5.10/Documentation/driver-api/
Dzorro.rst15 There are two types of Zorro buses, Zorro II and Zorro III:
20 - Zorro III is a 32-bit extension of Zorro II, which is backwards compatible
21 with Zorro II. The Zorro III address space lies outside the first 16 MB.
87 - Zorro III address space must be mapped explicitly using z_ioremap() first
/kernel/linux/linux-5.10/arch/m68k/amiga/
Dplatform.c22 /* Zorro II regions (on Zorro II/III) */
34 /* Zorro III regions (on Zorro III only) */
36 .name = "Zorro III exp",
41 .name = "Zorro III cfg",
/kernel/linux/linux-6.6/arch/m68k/amiga/
Dplatform.c22 /* Zorro II regions (on Zorro II/III) */
34 /* Zorro III regions (on Zorro III only) */
36 .name = "Zorro III exp",
41 .name = "Zorro III cfg",
/kernel/linux/linux-5.10/drivers/sbus/char/
DKconfig33 tristate "UltraSPARC-III bootbus i2c controller driver"
36 The BBC devices on the UltraSPARC III have two I2C controllers. The
64 another UltraSPARC-IIi-cEngine boardset with a 7-segment display,
/kernel/linux/linux-6.6/drivers/sbus/char/
DKconfig33 tristate "UltraSPARC-III bootbus i2c controller driver"
36 The BBC devices on the UltraSPARC III have two I2C controllers. The
64 another UltraSPARC-IIi-cEngine boardset with a 7-segment display,
/kernel/linux/linux-6.6/arch/x86/
DKconfig.cpu30 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
32 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
42 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
108 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
111 Select this for Intel chips based on the Pentium-III and
160 bool "K6/K6-II/K6-III"
238 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
/kernel/linux/linux-5.10/arch/x86/
DKconfig.cpu30 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
32 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
42 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
108 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
111 Select this for Intel chips based on the Pentium-III and
160 bool "K6/K6-II/K6-III"
238 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
/kernel/linux/linux-6.6/Documentation/powerpc/
Disa-versions.rst26 - PowerPC Operating Environment Architecture Book III v2.02
29 - PowerPC Operating Environment Architecture Book III v2.01
33 - PowerPC Operating Environment Architecture Book III v2.01
36 - PowerPC Operating Environment Architecture Book III v2.00
/kernel/linux/linux-6.6/drivers/cpufreq/
Dsparc-us3-cpufreq.c2 /* us3_cpufreq.c: UltraSPARC-III cpu frequency support
29 /* UltraSPARC-III has three dividers: 1, 2, and 32. These are controlled
150 .name = "UltraSPARC-III",
197 MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-III");
DKconfig.x86241 This adds the CPUFreq driver for certain mobile Intel Pentium III
242 (Coppermine), all mobile Intel Pentium III-M (Tualatin) and all
254 This adds the CPUFreq driver for certain mobile Intel Pentium III
255 (Coppermine), all mobile Intel Pentium III-M (Tualatin)
304 tristate "VIA Cyrix III Longhaul"
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/
Dti,ds90ub953.yaml7 title: Texas Instruments DS90UB953 FPD-Link III Serializer
13 The TI DS90UB953 is an FPD-Link III video serializer for MIPI CSI-2.
61 description: FPD-Link III output port
Dti,ds90ub913.yaml7 title: Texas Instruments DS90UB913 FPD-Link III Serializer
13 The TI DS90UB913 is an FPD-Link III video serializer for parallel video.
61 description: FPD-Link III output port
/kernel/linux/linux-5.10/drivers/cpufreq/
Dsparc-us3-cpufreq.c2 /* us3_cpufreq.c: UltraSPARC-III cpu frequency support
31 /* UltraSPARC-III has three dividers: 1, 2, and 32. These are controlled
187 strcpy(driver->name, "UltraSPARC-III"); in us3_freq_init()
221 MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-III");
DKconfig.x86202 This adds the CPUFreq driver for certain mobile Intel Pentium III
203 (Coppermine), all mobile Intel Pentium III-M (Tualatin) and all
215 This adds the CPUFreq driver for certain mobile Intel Pentium III
216 (Coppermine), all mobile Intel Pentium III-M (Tualatin)
265 tristate "VIA Cyrix III Longhaul"
/kernel/linux/linux-5.10/include/linux/
Drio_regs.h41 #define RIO_PEF_DEV32 0x00001000 /* [III] PE supports Common TRansport Dev32 */
42 #define RIO_PEF_EXT_RT 0x00000200 /* [III, 1.3] Extended route table support */
43 #define RIO_PEF_STD_RT 0x00000100 /* [III, 1.3] Standard route table support */
44 #define RIO_PEF_CTLS 0x00000010 /* [III] Common Transport Large System (< rev.3) */
45 #define RIO_PEF_DEV16 0x00000010 /* [III] PE Supports Common Transport Dev16 (rev.3) */
100 #define RIO_SWITCH_RT_LIMIT 0x34 /* [III, 1.3] Switch Route Table Destination ID Limit CAR */
156 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
160 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
161 #define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
203 #define RIO_EFB_SW_ROUTING_TBL 0x000E /* [III] Switch Routing Table Block */
/kernel/linux/linux-6.6/include/linux/
Drio_regs.h41 #define RIO_PEF_DEV32 0x00001000 /* [III] PE supports Common TRansport Dev32 */
42 #define RIO_PEF_EXT_RT 0x00000200 /* [III, 1.3] Extended route table support */
43 #define RIO_PEF_STD_RT 0x00000100 /* [III, 1.3] Standard route table support */
44 #define RIO_PEF_CTLS 0x00000010 /* [III] Common Transport Large System (< rev.3) */
45 #define RIO_PEF_DEV16 0x00000010 /* [III] PE Supports Common Transport Dev16 (rev.3) */
100 #define RIO_SWITCH_RT_LIMIT 0x34 /* [III, 1.3] Switch Route Table Destination ID Limit CAR */
156 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
160 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
161 #define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
203 #define RIO_EFB_SW_ROUTING_TBL 0x000E /* [III] Switch Routing Table Block */

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