| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
[all …]
|
| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
[all …]
|
| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/networking/device_drivers/can/freescale/ |
| D | flexcan.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
13 For most flexcan IP cores the driver supports 2 RX modes:
15 - FIFO
16 - mailbox
18 The older flexcan cores (integrated into the i.MX25, i.MX28, i.MX35
20 configured for RX-FIFO mode.
28 cores come up in a mode where RTR reception is possible.
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/platform/xilinx/ |
| D | xilinx-vip.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Video IP Core
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
17 #include <media/v4l2-subdev.h>
22 * Minimum and maximum width and height common to most video IP cores. IP
23 * cores with different requirements must define their own values.
31 * Pad IDs. IP cores with multiple inputs or outputs should define their own
37 /* Xilinx Video IP Control Registers */
68 /* Xilinx Video IP Timing Registers */
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/platform/xilinx/ |
| D | xilinx-vip.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Video IP Core
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
17 #include <media/v4l2-subdev.h>
22 * Minimum and maximum width and height common to most video IP cores. IP
23 * cores with different requirements must define their own values.
31 * Pad IDs. IP cores with with multiple inputs or outputs should define
37 /* Xilinx Video IP Control Registers */
68 /* Xilinx Video IP Timing Registers */
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/ti/ |
| D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/networking/device_drivers/ethernet/intel/ |
| D | i40e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
[all …]
|
| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/intel/ |
| D | i40e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
[all …]
|
| /kernel/linux/linux-5.10/arch/arc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
98 source "arch/arc/plat-tb10x/Kconfig"
99 source "arch/arc/plat-axs10x/Kconfig"
100 source "arch/arc/plat-hsdk/Kconfig"
112 The original ARC ISA of ARC600/700 cores
118 ISA for the Next Generation ARC-HS cores
143 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
145 -Caches: New Prog Model, Region Flush
146 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
[all …]
|
| /kernel/linux/linux-6.6/arch/arc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
102 The original ARC ISA of ARC600/700 cores
108 ISA for the Next Generation ARC-HS cores
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
128 -Caches: New Prog Model, Region Flush
129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/ti/ |
| D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-exynos/ |
| D | mcpm-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // Based on arch/arm/mach-vexpress/dcscb.c
7 #include <linux/arm-cci.h>
12 #include <linux/soc/samsung/exynos-regs-pmu.h>
38 "stmfd sp!, {fp, ip}\n\t"\
53 "ldmfd sp!, {fp, ip}" \
67 return -EINVAL; in exynos_cpu_powerup()
73 * This assumes the cluster number of the big cores(Cortex A15) in exynos_cpu_powerup()
74 * is 0 and the Little cores(Cortex A7) is 1. in exynos_cpu_powerup()
83 * Before we reset the Little cores, we should wait in exynos_cpu_powerup()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | gpio-grgpio.txt | 1 Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
25 For further information look in the documentation for the GLIB IP core library:
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | gpio-grgpio.txt | 1 Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
25 For further information look in the documentation for the GLIB IP core library:
|
| /kernel/linux/linux-6.6/Documentation/networking/device_drivers/ethernet/stmicro/ |
| D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
[all …]
|
| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/stmicro/ |
| D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,keystone-irq.txt | 1 Keystone 2 IRQ controller IP
3 On Keystone SOCs, DSP cores can send interrupts to ARM
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,keystone-irq.txt | 1 Keystone 2 IRQ controller IP
3 On Keystone SOCs, DSP cores can send interrupts to ARM
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/ |
| D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
23 accessible by means of the Baikal-T1 System Controller.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
23 accessible by means of the Baikal-T1 System Controller.
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "ETNAVIV (DRM support for Vivante GPU IP cores)"
|