| /kernel/linux/linux-5.10/drivers/net/ethernet/mscc/ |
| D | ocelot_police.c | 27 u32 cir = 0, cbs = 0, pir = 0, pbs = 0; in qos_policer_conf_set() local
33 pir = conf->pir; in qos_policer_conf_set()
60 pir += conf->cir; in qos_policer_conf_set()
63 if (pir == 0 && pbs == 0) { in qos_policer_conf_set()
64 /* Discard PIR frames */ in qos_policer_conf_set()
67 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
68 pir *= 3; /* 33 1/3 kbps */ in qos_policer_conf_set()
75 if (pir >= 100) { in qos_policer_conf_set()
77 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
78 pir *= 3; /* 33 1/3 fps */ in qos_policer_conf_set()
[all …]
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| D | ocelot_police.h | 28 u32 pir; /* PIR in kbps/fps */ member
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| /kernel/linux/linux-6.6/drivers/net/ethernet/mscc/ |
| D | ocelot_police.c | 27 u32 cir = 0, cbs = 0, pir = 0, pbs = 0; in qos_policer_conf_set() local
33 pir = conf->pir; in qos_policer_conf_set()
60 pir += conf->cir; in qos_policer_conf_set()
63 if (pir == 0 && pbs == 0) { in qos_policer_conf_set()
64 /* Discard PIR frames */ in qos_policer_conf_set()
67 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
68 pir *= 3; /* 33 1/3 kbps */ in qos_policer_conf_set()
75 if (pir >= 100) { in qos_policer_conf_set()
77 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
78 pir *= 3; /* 33 1/3 fps */ in qos_policer_conf_set()
[all …]
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| D | ocelot_police.h | 29 u32 pir; /* PIR in kbps/fps */ member
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| /kernel/linux/linux-5.10/arch/x86/kvm/vmx/ |
| D | posted_intr.h | 10 u32 pir[8]; /* Posted interrupt requested */ member
45 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); in pi_test_and_set_pir()
50 return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS); in pi_is_pir_empty()
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| /kernel/linux/linux-6.6/arch/x86/kvm/vmx/ |
| D | posted_intr.h | 12 u32 pir[8]; /* Posted interrupt requested */ member
53 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); in pi_test_and_set_pir()
58 return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS); in pi_is_pir_empty()
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/powernv/ |
| D | opal-core.c | 36 /* PIR value of crashing CPU */
111 static void fill_prstatus(struct elf_prstatus *prstatus, int pir, in fill_prstatus() argument
118 * Overload PID with PIR value. in fill_prstatus()
119 * As a PIR value could also be '0', add an offset of '100' in fill_prstatus()
120 * to every PIR to avoid misinterpretations in GDB. in fill_prstatus()
122 prstatus->pr_pid = cpu_to_be32(100 + pir); in fill_prstatus()
129 if (pir == oc_conf->crashing_cpu) { in fill_prstatus()
260 thread_pir = be32_to_cpu(thdr->pir); in opalcore_append_cpu_notes()
262 pr_debug("[%04d] PIR: 0x%x, core state: 0x%02x\n", in opalcore_append_cpu_notes()
277 pr_debug("PIR 0x%x - R1 : 0x%llx, NIP : 0x%llx\n", thread_pir, in opalcore_append_cpu_notes()
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| D | idle.c | 81 uint64_t pir = get_hard_smp_processor_id(cpu); in pnv_save_sprs_for_deep_states() local
84 rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); in pnv_save_sprs_for_deep_states()
88 rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); in pnv_save_sprs_for_deep_states()
93 rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); in pnv_save_sprs_for_deep_states()
97 rc = opal_slw_set_reg(pir, in pnv_save_sprs_for_deep_states()
107 rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); in pnv_save_sprs_for_deep_states()
111 rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); in pnv_save_sprs_for_deep_states()
121 rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); in pnv_save_sprs_for_deep_states()
125 rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); in pnv_save_sprs_for_deep_states()
129 rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); in pnv_save_sprs_for_deep_states()
[all …]
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| D | opal-fadump.c | 462 thread_pir = be32_to_cpu(thdr->pir); in opal_fadump_build_cpu_notes()
463 pr_debug("[%04d] PIR: 0x%x, core state: 0x%02x\n", in opal_fadump_build_cpu_notes()
476 pr_debug("Crashing CPU PIR: 0x%x - R1 : 0x%lx, NIP : 0x%lx\n", in opal_fadump_build_cpu_notes()
494 pr_debug("CPU PIR: 0x%x - R1 : 0x%lx, NIP : 0x%lx\n", in opal_fadump_build_cpu_notes()
605 * CPU's PIR instead to plug the appropriate register data for in opal_fadump_trigger()
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| D | opal-hmi.c | 79 printk("%s CPU PIR: %08x\n", level, in print_core_checkstop_reason()
80 be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); in print_core_checkstop_reason()
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| /kernel/linux/linux-6.6/arch/powerpc/platforms/powernv/ |
| D | opal-core.c | 36 /* PIR value of crashing CPU */
111 static void __init fill_prstatus(struct elf_prstatus *prstatus, int pir, in fill_prstatus() argument
118 * Overload PID with PIR value. in fill_prstatus()
119 * As a PIR value could also be '0', add an offset of '100' in fill_prstatus()
120 * to every PIR to avoid misinterpretations in GDB. in fill_prstatus()
122 prstatus->common.pr_pid = cpu_to_be32(100 + pir); in fill_prstatus()
129 if (pir == oc_conf->crashing_cpu) { in fill_prstatus()
260 thread_pir = be32_to_cpu(thdr->pir); in opalcore_append_cpu_notes()
262 pr_debug("[%04d] PIR: 0x%x, core state: 0x%02x\n", in opalcore_append_cpu_notes()
277 pr_debug("PIR 0x%x - R1 : 0x%llx, NIP : 0x%llx\n", thread_pir, in opalcore_append_cpu_notes()
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| D | idle.c | 81 uint64_t pir = get_hard_smp_processor_id(cpu); in pnv_save_sprs_for_deep_states() local
84 rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); in pnv_save_sprs_for_deep_states()
88 rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); in pnv_save_sprs_for_deep_states()
93 rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); in pnv_save_sprs_for_deep_states()
97 rc = opal_slw_set_reg(pir, in pnv_save_sprs_for_deep_states()
107 rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); in pnv_save_sprs_for_deep_states()
111 rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); in pnv_save_sprs_for_deep_states()
121 rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); in pnv_save_sprs_for_deep_states()
125 rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); in pnv_save_sprs_for_deep_states()
129 rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); in pnv_save_sprs_for_deep_states()
[all …]
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| D | opal-fadump.c | 462 thread_pir = be32_to_cpu(thdr->pir); in opal_fadump_build_cpu_notes()
463 pr_debug("[%04d] PIR: 0x%x, core state: 0x%02x\n", in opal_fadump_build_cpu_notes()
476 pr_debug("Crashing CPU PIR: 0x%x - R1 : 0x%lx, NIP : 0x%lx\n", in opal_fadump_build_cpu_notes()
494 pr_debug("CPU PIR: 0x%x - R1 : 0x%lx, NIP : 0x%lx\n", in opal_fadump_build_cpu_notes()
605 * CPU's PIR instead to plug the appropriate register data for in opal_fadump_trigger()
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| D | opal-hmi.c | 79 printk("%s CPU PIR: %08x\n", level, in print_core_checkstop_reason()
80 be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); in print_core_checkstop_reason()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/proximity/ |
| D | murata,irsd200.yaml | 7 title: Murata IRS-D200 PIR sensor
13 PIR sensor for human detection.
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| /kernel/linux/linux-6.6/arch/powerpc/include/uapi/asm/ |
| D | kvm_para.h | 59 __u32 pir; member
90 /* MASn, ESR, PIR, and high SPRGs */
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| /kernel/linux/linux-5.10/arch/powerpc/include/uapi/asm/ |
| D | kvm_para.h | 59 __u32 pir; member
90 /* MASn, ESR, PIR, and high SPRGs */
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| /kernel/linux/linux-6.6/drivers/net/ethernet/freescale/enetc/ |
| D | enetc_cbdr.c | 28 cbdr->pir = hw->reg + ENETC_SICBDRPIR; in enetc_setup_cbdr()
40 enetc_wr_reg(cbdr->pir, cbdr->next_to_clean); in enetc_setup_cbdr()
113 enetc_wr_reg(ring->pir, i); in enetc_send_cmd()
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| /kernel/linux/linux-6.6/drivers/iio/proximity/ |
| D | Kconfig | 36 tristate "Murata IRS-D200 PIR sensor"
42 Say Y here to build a driver for the Murata IRS-D200 PIR sensor.
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | head_64.S | 58 * generic_secondary_smp_init, with PIR in r3.
60 * directed by the "start-cpu" RTS call, with PIR in r3.
66 * is at generic_secondary_smp_init, with PIR in r3.
278 * Fix PIR to match the linear numbering in the device tree.
280 * On e6500, the reset value of PIR uses the low three bits for
288 * scenario, and PIR is already set to the correct value. This
292 * at the old PIR value which state it's in, since the same value
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| /kernel/linux/linux-6.6/arch/powerpc/kvm/ |
| D | e500_emulate.c | 67 int pir = param & PPC_DBELL_PIR_MASK; in kvmppc_e500_emul_msgsnd() local
75 int cpir = cvcpu->arch.shared->pir; in kvmppc_e500_emul_msgsnd()
76 if ((param & PPC_DBELL_MSG_BRDCAST) || (cpir == pir)) { in kvmppc_e500_emul_msgsnd()
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| /kernel/linux/linux-5.10/arch/powerpc/kvm/ |
| D | e500_emulate.c | 67 int pir = param & PPC_DBELL_PIR_MASK; in kvmppc_e500_emul_msgsnd() local
75 int cpir = cvcpu->arch.shared->pir; in kvmppc_e500_emul_msgsnd()
76 if ((param & PPC_DBELL_MSG_BRDCAST) || (cpir == pir)) { in kvmppc_e500_emul_msgsnd()
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| /kernel/linux/linux-6.6/arch/powerpc/kernel/ |
| D | head_64.S | 63 * generic_secondary_smp_init, with PIR in r3.
65 * directed by the "start-cpu" RTS call, with PIR in r3.
71 * is at generic_secondary_smp_init, with PIR in r3.
282 * Fix PIR to match the linear numbering in the device tree.
284 * On e6500, the reset value of PIR uses the low three bits for
292 * scenario, and PIR is already set to the correct value. This
296 * at the old PIR value which state it's in, since the same value
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| /kernel/linux/linux-5.10/arch/x86/kvm/ |
| D | lapic.h | 93 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
94 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
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| /kernel/linux/linux-6.6/arch/x86/kvm/ |
| D | lapic.h | 108 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
109 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
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