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/kernel/linux/linux-5.10/arch/arm/mach-zynq/
Dslcr.c3 * Xilinx SLCR driver
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
47 * zynq_slcr_read - Read a register in SLCR block
49 * @val: Pointer to value to be read from SLCR
50 * @offset: Register offset in SLCR block
60 * zynq_slcr_unlock - Unlock SLCR registers
189 * zynq_early_slcr_init - Early slcr init function
193 * Called very early during boot from platform code to unlock SLCR.
199 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); in zynq_early_slcr_init()
[all …]
DMakefile7 obj-y := common.o slcr.o pm.o
Dplatsmp.c36 /* MS: Expectation that SLCR are directly map and accessible */ in zynq_cpun_start()
/kernel/linux/linux-6.6/arch/arm/mach-zynq/
Dslcr.c3 * Xilinx SLCR driver
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
47 * zynq_slcr_read - Read a register in SLCR block
49 * @val: Pointer to value to be read from SLCR
50 * @offset: Register offset in SLCR block
60 * zynq_slcr_unlock - Unlock SLCR registers
189 * zynq_early_slcr_init - Early slcr init function
193 * Called very early during boot from platform code to unlock SLCR.
199 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); in zynq_early_slcr_init()
[all …]
DMakefile7 obj-y := common.o slcr.o pm.o
Dplatsmp.c36 /* MS: Expectation that SLCR are directly map and accessible */ in zynq_cpun_start()
/kernel/linux/linux-5.10/drivers/reset/
Dreset-zynq.c21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg); in zynq_reset_status()
99 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
101 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
102 dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); in zynq_reset_probe()
103 return PTR_ERR(priv->slcr); in zynq_reset_probe()
/kernel/linux/linux-6.6/drivers/reset/
Dreset-zynq.c21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg); in zynq_reset_status()
98 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
100 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
101 dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); in zynq_reset_probe()
102 return PTR_ERR(priv->slcr); in zynq_reset_probe()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
21 syscon = <&slcr>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
21 syscon = <&slcr>;
/kernel/linux/linux-6.6/drivers/fpga/
Dzynq-fpga.c27 /* Offsets into SLCR regmap */
110 /* Masks for controlling stuff in SLCR */
127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
569 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
571 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
[all …]
/kernel/linux/linux-5.10/drivers/fpga/
Dzynq-fpga.c27 /* Offsets into SLCR regmap */
110 /* Masks for controlling stuff in SLCR */
127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
571 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
573 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/fpga/
Dxilinx-zynq-fpga-mgr.txt9 - syscon: phandle for access to SLCR registers
18 syscon = <&slcr>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dxlnx,zynq-pinctrl.txt5 - syscon: phandle to SLCR
6 - reg: Offset and length of pinctrl space in SLCR
81 syscon = <&slcr>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/
Dxilinx-zynq-fpga-mgr.yaml32 Phandle to syscon block which provide access to SLCR registers
51 syscon = <&slcr>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dzynq-7000.dtsi275 slcr: slcr@f8000000 { label
278 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
303 syscon = <&slcr>;
309 syscon = <&slcr>;
338 syscon = <&slcr>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dxlnx,zynq-pinctrl.yaml34 description: Specifies the base address and size of the SLCR space.
39 phandle to the SLCR.
186 syscon = <&slcr>;
/kernel/linux/linux-6.6/arch/arm/boot/dts/xilinx/
Dzynq-7000.dtsi310 slcr: slcr@f8000000 { label
313 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
338 syscon = <&slcr>;
344 syscon = <&slcr>;
373 syscon = <&slcr>;
/kernel/linux/linux-5.10/drivers/clk/zynq/
Dclkc.c584 struct device_node *slcr; in zynq_clock_init() local
598 slcr = of_get_parent(np); in zynq_clock_init()
600 if (slcr->data) { in zynq_clock_init()
601 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
604 of_node_put(slcr); in zynq_clock_init()
610 of_node_put(slcr); in zynq_clock_init()
/kernel/linux/linux-6.6/drivers/clk/zynq/
Dclkc.c582 struct device_node *slcr; in zynq_clock_init() local
596 slcr = of_get_parent(np); in zynq_clock_init()
598 if (slcr->data) { in zynq_clock_init()
599 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
602 of_node_put(slcr); in zynq_clock_init()
608 of_node_put(slcr); in zynq_clock_init()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/xilinx/
Dxlnx,vcu.txt16 1. vcu slcr
/kernel/linux/linux-5.10/drivers/pci/controller/
Dpcie-xilinx-cpm.c104 * @cpm_base: CPM System Level Control and Status Register(SLCR) Base
290 * CPM SLCR block. in xilinx_cpm_pcie_event_flow()
483 * CPM SLCR block. in xilinx_cpm_pcie_init_port()
/kernel/linux/linux-6.6/drivers/pci/controller/
Dpcie-xilinx-cpm.c121 * @cpm_base: CPM System Level Control and Status Register(SLCR) Base
315 * CPM SLCR block. in xilinx_cpm_pcie_event_flow()
508 * CPM SLCR block. in xilinx_cpm_pcie_init_port()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dzynq-7000.txt17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dzynq-7000.txt17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >

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