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Searched +full:ahci +full:- +full:glue (Results 1 – 23 of 23) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/socionext/
Dsocionext,uniphier-ahci-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC AHCI glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
14 logic handling signals to AHCI host controller inside AHCI component.
19 - enum:
20 - socionext,uniphier-pro4-ahci-glue
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Duniphier-reset.txt1 UniPhier glue reset controller
4 Peripheral core reset in glue layer
5 -----------------------------------
7 Some peripheral core reset belongs to its own glue layer. Before using
12 - compatible: Should be
13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
16 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
17 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-ahci-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier AHCI PHY
11 AHCI controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pxs2-ahci-phy
20 - socionext,uniphier-pxs3-ahci-phy
25 "#phy-cells":
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/ata/
Dahci-platform.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
26 - brcm,iproc-ahci
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dsocionext,uniphier-glue-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
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/kernel/linux/linux-5.10/drivers/reset/
Dreset-uniphier-glue.c1 // SPDX-License-Identifier: GPL-2.0
3 // reset-uniphier-glue.c - Glue layer reset driver for UniPhier
12 #include <linux/reset/reset-simple.h>
33 struct device *dev = &pdev->dev; in uniphier_glue_reset_probe()
42 return -ENOMEM; in uniphier_glue_reset_probe()
44 priv->data = of_device_get_match_data(dev); in uniphier_glue_reset_probe()
45 if (WARN_ON(!priv->data || priv->data->nclks > MAX_CLKS || in uniphier_glue_reset_probe()
46 priv->data->nrsts > MAX_RSTS)) in uniphier_glue_reset_probe()
47 return -EINVAL; in uniphier_glue_reset_probe()
51 priv->rdata.membase = devm_ioremap_resource(dev, res); in uniphier_glue_reset_probe()
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/kernel/linux/linux-6.6/drivers/reset/
Dreset-uniphier-glue.c1 // SPDX-License-Identifier: GPL-2.0
3 // reset-uniphier-glue.c - Glue layer reset driver for UniPhier
12 #include <linux/reset/reset-simple.h>
35 clk_bulk_disable_unprepare(priv->data->nclks, priv->clk); in uniphier_clk_disable()
42 reset_control_bulk_assert(priv->data->nrsts, priv->rst); in uniphier_rst_assert()
47 struct device *dev = &pdev->dev; in uniphier_glue_reset_probe()
54 return -ENOMEM; in uniphier_glue_reset_probe()
56 priv->data = of_device_get_match_data(dev); in uniphier_glue_reset_probe()
57 if (WARN_ON(!priv->data || priv->data->nclks > MAX_CLKS || in uniphier_glue_reset_probe()
58 priv->data->nrsts > MAX_RSTS)) in uniphier_glue_reset_probe()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/cavium/
Dsata-uctl.txt1 * UCTL SATA controller glue
4 and the SATA AHCI host controller (UAHC). It performs the following functions:
5 - provides interfaces for the applications to access the UAHC AHCI
7 - provides a bridge for UAHC to fetch AHCI command table entries and data
9 - posts interrupts to the CIU.
10 - contains registers that:
11 - control the behavior of the UAHC
12 - control the clock/reset generation to UAHC
13 - control endian swapping for all UAHC registers and DMA accesses
17 - compatible: "cavium,octeon-7130-sata-uctl"
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mips/cavium/
Dsata-uctl.txt1 * UCTL SATA controller glue
4 and the SATA AHCI host controller (UAHC). It performs the following functions:
5 - provides interfaces for the applications to access the UAHC AHCI
7 - provides a bridge for UAHC to fetch AHCI command table entries and data
9 - posts interrupts to the CIU.
10 - contains registers that:
11 - control the behavior of the UAHC
12 - control the clock/reset generation to UAHC
13 - control endian swapping for all UAHC registers and DMA accesses
17 - compatible: "cavium,octeon-7130-sata-uctl"
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/kernel/linux/linux-6.6/arch/arm/boot/dts/socionext/
Duniphier-pro4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
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Duniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
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/kernel/linux/linux-6.6/drivers/ata/
Dahci_octeon.c2 * SATA glue for Cavium Octeon III SOCs.
9 * Copyright (C) 2010-2015 Cavium Networks
14 #include <linux/dma-mapping.h>
32 struct device *dev = &pdev->dev; in ahci_octeon_probe()
33 struct device_node *node = dev->of_node; in ahci_octeon_probe()
61 return -ENODEV; in ahci_octeon_probe()
66 dev_err(dev, "failed to add ahci-platform core\n"); in ahci_octeon_probe()
74 { .compatible = "cavium,octeon-7130-sata-uctl", },
82 .name = "octeon-ahci",
Dahci_mvebu.c2 * AHCI glue platform driver for Marvell EBU SOCs
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
20 #include "ahci.h"
22 #define DRV_NAME "ahci-mvebu"
42 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i)); in ahci_mvebu_mbus_config()
43 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
44 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i)); in ahci_mvebu_mbus_config()
47 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
48 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
50 writel((cs->mbus_attr << 8) | in ahci_mvebu_mbus_config()
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/kernel/linux/linux-5.10/drivers/ata/
Dahci_octeon.c2 * SATA glue for Cavium Octeon III SOCs.
9 * Copyright (C) 2010-2015 Cavium Networks
14 #include <linux/dma-mapping.h>
33 struct device *dev = &pdev->dev; in ahci_octeon_probe()
34 struct device_node *node = dev->of_node; in ahci_octeon_probe()
41 base = devm_ioremap_resource(&pdev->dev, res); in ahci_octeon_probe()
64 return -ENODEV; in ahci_octeon_probe()
69 dev_err(dev, "failed to add ahci-platform core\n"); in ahci_octeon_probe()
82 { .compatible = "cavium,octeon-7130-sata-uctl", },
91 .name = "octeon-ahci",
Dahci_mvebu.c2 * AHCI glue platform driver for Marvell EBU SOCs
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
20 #include "ahci.h"
22 #define DRV_NAME "ahci-mvebu"
42 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i)); in ahci_mvebu_mbus_config()
43 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
44 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i)); in ahci_mvebu_mbus_config()
47 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
48 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
50 writel((cs->mbus_attr << 8) | in ahci_mvebu_mbus_config()
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/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Ddm816x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/bus/ti-sysc.h>
4 #include <dt-bindings/clock/dm816.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/omap.h>
10 interrupt-parent = <&intc>;
11 #address-cells = <1>;
12 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ddm816x.dtsi7 #include <dt-bindings/bus/ti-sysc.h>
8 #include <dt-bindings/clock/dm816.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/omap.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
33 compatible = "arm,cortex-a8";
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Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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/kernel/linux/patches/linux-5.10/hispark_taurus_patch/
Dhispark_taurus.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -650,6 +650,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
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/kernel/linux/patches/linux-4.19/hispark_taurus_patch/
Dhispark_taurus.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -330,7 +330,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -751,6 +751,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
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/kernel/linux/linux-6.6/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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