| /kernel/linux/linux-6.6/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
72 /* Axi DMA Register definitions */
144 /* Axi Ethernet registers definition */
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
179 /* Bit Masks for Axi Ethernet RAF register */
198 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
200 /* Transmit inter-frame gap adjustment value */
203 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
[all …]
|
| /kernel/linux/linux-5.10/arch/arc/plat-axs10x/ |
| D | axs10x.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
12 #include <asm/asm-offsets.h>
34 * --------------------- in axs10x_enable_gpio_intc_wire()
35 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
36 * --------------------- in axs10x_enable_gpio_intc_wire()
38 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
39 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
40 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
44 * ------------------------ in axs10x_enable_gpio_intc_wire()
[all …]
|
| /kernel/linux/linux-6.6/arch/arc/plat-axs10x/ |
| D | axs10x.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
33 * --------------------- in axs10x_enable_gpio_intc_wire()
34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
35 * --------------------- in axs10x_enable_gpio_intc_wire()
37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
39 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
43 * ------------------------ in axs10x_enable_gpio_intc_wire()
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
72 /* Axi DMA Register definitions */
144 /* Axi Ethernet registers definition */
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
179 /* Bit Masks for Axi Ethernet RAF register */
198 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
200 /* Transmit inter-frame gap adjustment value */
203 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/imx/ |
| D | fsl-imx-drm.txt | 8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,imx-display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/imx/ |
| D | fsl-imx-drm.txt | 8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/baikal-t1/ |
| D | clk-ccu-div.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/bt1-ccu.h>
28 #include "ccu-div.h"
29 #include "ccu-rst.h"
62 .base = _base, \
74 .base = _base, \
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/adi/ |
| D | axi-spdif.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
102 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_hw_params()
112 snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL); in axi_spdif_dai_probe()
[all …]
|
| D | axi-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
63 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_trigger()
80 return -EINVAL; in axi_i2s_trigger()
83 regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); in axi_i2s_trigger()
97 word_size = AXI_I2S_BITS_PER_FRAME / 2 - 1; in axi_i2s_hw_params()
98 bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1; in axi_i2s_hw_params()
100 regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) | in axi_i2s_hw_params()
113 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_startup()
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/adi/ |
| D | axi-spdif.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
102 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_hw_params()
112 snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL); in axi_spdif_dai_probe()
[all …]
|
| D | axi-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
63 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_trigger()
80 return -EINVAL; in axi_i2s_trigger()
83 regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); in axi_i2s_trigger()
97 word_size = AXI_I2S_BITS_PER_FRAME / 2 - 1; in axi_i2s_hw_params()
98 bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1; in axi_i2s_hw_params()
100 regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) | in axi_i2s_hw_params()
113 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_startup()
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
108 (((aperture) - 2) << ((bar) * 8))
129 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
134 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
142 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
169 /* Region r AXI Region Base Address Register 0 */
174 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
176 /* Region r AXI Region Base Address Register 1 */
180 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/microchip/ |
| D | clk-mpfs.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/microchip,mpfs-clock.h>
35 void __iomem *base; member
41 void __iomem *base; member
99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
101 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_recalc_rate()
117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_round_rate()
[all …]
|
| /kernel/linux/linux-6.6/drivers/pci/controller/cadence/ |
| D | pcie-cadence.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
117 (((aperture) - 2) << ((bar) * 8))
144 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
149 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
157 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
184 /* Region r AXI Region Base Address Register 0 */
189 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
191 /* Region r AXI Region Base Address Register 1 */
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | adi,axi-spi-engine.txt | 1 Analog Devices AXI SPI Engine controller Device Tree Bindings
4 - compatible : Must be "adi,axi-spi-engine-1.00.a""
5 - reg : Physical base address and size of the register map.
6 - interrupts : Property with a value describing the interrupt
8 - clock-names : List of input clock names - "s_axi_aclk", "spi_clk"
9 - clocks : Clock phandles and specifiers (See clock bindings for
10 details on clock-names and clocks).
11 - #address-cells : Must be <1>
12 - #size-cells : Must be <0>
16 master. They follow the generic SPI bindings as outlined in spi-bus.txt.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | adi,axi-spi-engine.txt | 1 Analog Devices AXI SPI Engine controller Device Tree Bindings
4 - compatible : Must be "adi,axi-spi-engine-1.00.a""
5 - reg : Physical base address and size of the register map.
6 - interrupts : Property with a value describing the interrupt
8 - clock-names : List of input clock names - "s_axi_aclk", "spi_clk"
9 - clocks : Clock phandles and specifiers (See clock bindings for
10 details on clock-names and clocks).
11 - #address-cells : Must be <1>
12 - #size-cells : Must be <0>
16 master. They follow the generic SPI bindings as outlined in spi-bus.txt.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | fsl-pxp.txt | 4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
10 - compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
12 - reg: the register base and size for the device registers
13 - interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
14 - clock-names: should be "axi"
15 - clocks: the PXP AXI clock
20 compatible = "fsl,imx6ull-pxp";
24 clock-names = "axi";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | ahci-mtk.txt | 4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/ata/ |
| D | ahci-mtk.txt | 4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
[all …]
|
| /kernel/linux/linux-5.10/drivers/hwtracing/coresight/ |
| D | coresight-catu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "coresight-priv.h"
13 /* Register offset from base */
41 * AXI - ARPROT bits:
42 * See AMBA AXI & ACE Protocol specification (ARM IHI 0022E)
45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
47 * Bit 2: 0 - Data access, 1 - instruction access.
64 void __iomem *base; member
73 return coresight_read_reg_pair(drvdata->base, offset, -1); \
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac1000_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
19 static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwmac1000_dma_axi() argument
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac1000_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
19 static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwmac1000_dma_axi() argument
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
[all …]
|