Searched +full:axi +full:- +full:can +full:- +full:1 (Results 1 – 25 of 362) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
2 It can be configured to have one channel or two channels. If configured
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
15 target devices. It can be configured to have up to 16 independent transmit
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
2 It can be configured to have one channel or two channels. If configured
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
15 target devices. It can be configured to have up to 16 independent transmit
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/ |
| D | xilinx,can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Xilinx Axi CAN/Zynq CANPS controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/ |
| D | xlnx,pr-decoupler.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
14 decouplers/fpga bridges. The controller can decouple/disable the bridges
16 can also couple / enable the bridges which allows traffic to pass through the
18 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
19 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
20 later ones are described in this binding. Each clock domain can be also
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
20 later ones are described in this binding. Each clock domain can be also
[all …]
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| D | adi,axi-clkgen.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Michael Hennerich <michael.hennerich@analog.com>
15 that can be synthesized on various FPGA platforms.
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
6 a character device that can be read/written to with standard
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
[all …]
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| /kernel/linux/linux-6.6/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
6 a character device that can be read/written to with standard
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/hwmon/ |
| D | adi,axi-fan-control.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Analog Devices AXI FAN Control Device Tree Bindings
11 - Nuno Sá <nuno.sa@analog.com>
14 Bindings for the Analog Devices AXI FAN Control driver. Spefications of the
15 core can be found in:
22 - adi,axi-fan-control-1.00.a
25 maxItems: 1
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/hwmon/ |
| D | adi,axi-fan-control.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Analog Devices AXI FAN Control
11 - Nuno Sá <nuno.sa@analog.com>
14 Bindings for the Analog Devices AXI FAN Control driver. Specifications of the
15 core can be found in:
22 - adi,axi-fan-control-1.00.a
25 maxItems: 1
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/ |
| D | xilinx-xadc.txt | 6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
10 on all series 7 platforms and is a softmacro with a AXI interface. This binding
16 communication. Xilinx provides a standard IP core that can be used to access the
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
3 The core can be generated with transmit (playback), only receive
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
19 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
3 The core can be generated with transmit (playback), only receive
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
19 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
18 (devices). This is needed since some hardware details can't be auto
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
18 (devices). This is needed since some hardware details can't be auto
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
[all …]
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| /kernel/linux/linux-6.6/Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 17 (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
19 hardware supported that can be used with perf tool, see /sys/bus/event_source/
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
31 in the driver. You also can dump info from userspace, filter in "caps" directory
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
34 value 1 for supported.
[all …]
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| /kernel/linux/linux-5.10/Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 17 (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
19 hardware supported that can be used with perf tool, see /sys/bus/event_source/
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
31 in the driver. You also can dump info from userspace, filter in "caps" directory
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
34 value 1 for supported.
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx Axi Ethernet device driver
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
13 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
17 * - Add Axi Fifo support.
18 * - Factor out Axi DMA code into separate driver.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
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| /kernel/linux/linux-5.10/drivers/dma/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 DMA engines can do asynchronous data transfers without
11 involving the host CPU. Currently, this framework can be
73 Say yes if your platform has a PL08x DMAC device which can
103 tristate "Analog Devices AXI-DMAC DMA support"
109 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
129 bool "ST-Ericsson COH901318 DMA support"
133 Enable support for ST-Ericsson COH 901 318 DMA.
149 devices which can use the DMA controller, say Y or M here.
152 tristate "SA-11x0 DMA support"
[all …]
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| /kernel/linux/linux-6.6/drivers/dma/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 DMA engines can do asynchronous data transfers without
11 involving the host CPU. Currently, this framework can be
73 Say yes if your platform has a PL08x DMAC device which can
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
151 devices which can use the DMA controller, say Y or M here.
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/freescale/fman/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 Freescale Data-Path Acceleration Architecture Frame Manager
24 The FMAN internal queue can overflow when FMAN splits single
26 such that more than 17 AXI transactions are in flight from FMAN
27 to interconnect. When the FMAN internal queue overflows, it can
28 stall further packet processing. The issue can occur with any
30 1. FMAN AXI transaction crosses 4K address boundary (Errata
32 2. FMAN DMA address for an AXI transaction is not 16 byte
33 aligned, i.e. the last 4 bits of an address are non-zero
40 stress with multiple ports injecting line-rate traffic.
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/freescale/fman/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 Freescale Data-Path Acceleration Architecture Frame Manager
23 The FMAN internal queue can overflow when FMAN splits single
25 such that more than 17 AXI transactions are in flight from FMAN
26 to interconnect. When the FMAN internal queue overflows, it can
27 stall further packet processing. The issue can occur with any
29 1. FMAN AXI transaction crosses 4K address boundary (Errata
31 2. FMAN DMA address for an AXI transaction is not 16 byte
32 aligned, i.e. the last 4 bits of an address are non-zero
39 stress with multiple ports injecting line-rate traffic.
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