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/kernel/linux/linux-6.6/sound/soc/codecs/
Dwm8990.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8990.c -- WM8990 ALSA Soc Audio driver
37 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
39 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
41 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
43 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
45 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
47 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
54 (struct soc_mixer_control *)kcontrol->private_value; in wm899x_outpga_put_volsw_vu()
55 int reg = mc->reg; in wm899x_outpga_put_volsw_vu()
[all …]
Dwm8991.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8991.c -- WM8991 ALSA Soc Audio driver
5 * Copyright 2007-2010 Wolfson Microelectronics PLC.
23 #include <sound/soc-dapm.h>
36 { 1, 0x0000 }, /* R1 - Power Management (1) */
37 { 2, 0x6000 }, /* R2 - Power Management (2) */
38 { 3, 0x0000 }, /* R3 - Power Management (3) */
39 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
40 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
41 { 6, 0x01C8 }, /* R6 - Clocking (1) */
[all …]
Dwm8400.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8400.c -- WM8400 ALSA Soc Audio driver
5 * Copyright 2008-11 Wolfson Microelectronics PLC.
18 #include <linux/mfd/wm8400-audio.h>
19 #include <linux/mfd/wm8400-private.h>
67 wm8400_reset_codec_reg_cache(wm8400->wm8400); in wm8400_component_reset()
70 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
72 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
74 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
76 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
[all …]
Disabelle.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * isabelle.c - Low power high fidelity audio codec driver
22 #include <sound/soc-dapm.h>
342 static const DECLARE_TLV_DB_SCALE(afm_amp_tlv, -3300, 300, 0);
343 static const DECLARE_TLV_DB_SCALE(dac_tlv, -1200, 200, 0);
344 static const DECLARE_TLV_DB_SCALE(hf_tlv, -5000, 200, 0);
346 /* from -63 to 0 dB in 1 dB steps */
347 static const DECLARE_TLV_DB_SCALE(dpga_tlv, -6300, 100, 1);
349 /* from -63 to 9 dB in 1 dB steps */
350 static const DECLARE_TLV_DB_SCALE(rx_tlv, -6300, 100, 1);
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dwm8990.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8990.c -- WM8990 ALSA Soc Audio driver
37 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
39 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
41 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
43 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
45 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
47 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
54 (struct soc_mixer_control *)kcontrol->private_value; in wm899x_outpga_put_volsw_vu()
55 int reg = mc->reg; in wm899x_outpga_put_volsw_vu()
[all …]
Dwm8991.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8991.c -- WM8991 ALSA Soc Audio driver
5 * Copyright 2007-2010 Wolfson Microelectronics PLC.
23 #include <sound/soc-dapm.h>
36 { 1, 0x0000 }, /* R1 - Power Management (1) */
37 { 2, 0x6000 }, /* R2 - Power Management (2) */
38 { 3, 0x0000 }, /* R3 - Power Management (3) */
39 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
40 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
41 { 6, 0x01C8 }, /* R6 - Clocking (1) */
[all …]
Dwm8400.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8400.c -- WM8400 ALSA Soc Audio driver
5 * Copyright 2008-11 Wolfson Microelectronics PLC.
18 #include <linux/mfd/wm8400-audio.h>
19 #include <linux/mfd/wm8400-private.h>
67 wm8400_reset_codec_reg_cache(wm8400->wm8400); in wm8400_component_reset()
70 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
72 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
74 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
76 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
[all …]
Disabelle.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * isabelle.c - Low power high fidelity audio codec driver
22 #include <sound/soc-dapm.h>
342 static const DECLARE_TLV_DB_SCALE(afm_amp_tlv, -3300, 300, 0);
343 static const DECLARE_TLV_DB_SCALE(dac_tlv, -1200, 200, 0);
344 static const DECLARE_TLV_DB_SCALE(hf_tlv, -5000, 200, 0);
346 /* from -63 to 0 dB in 1 dB steps */
347 static const DECLARE_TLV_DB_SCALE(dpga_tlv, -6300, 100, 1);
349 /* from -63 to 9 dB in 1 dB steps */
350 static const DECLARE_TLV_DB_SCALE(rx_tlv, -6300, 100, 1);
[all …]
/kernel/linux/linux-6.6/drivers/regulator/
Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
30 bool bypass; member
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
86 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
[all …]
/kernel/linux/linux-5.10/drivers/regulator/
Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
30 bool bypass; member
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
86 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
[all …]
/kernel/linux/linux-5.10/drivers/base/regmap/
Dregcache.c1 // SPDX-License-Identifier: GPL-2.0
34 if (!map->num_reg_defaults_raw) in regcache_hw_init()
35 return -EINVAL; in regcache_hw_init()
38 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) in regcache_hw_init()
39 if (regmap_readable(map, i * map->reg_stride) && in regcache_hw_init()
40 !regmap_volatile(map, i * map->reg_stride)) in regcache_hw_init()
43 /* all registers are unreadable or volatile, so just bypass */ in regcache_hw_init()
45 map->cache_bypass = true; in regcache_hw_init()
49 map->num_reg_defaults = count; in regcache_hw_init()
50 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), in regcache_hw_init()
[all …]
/kernel/linux/linux-5.10/drivers/clk/ti/
Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
[all …]
/kernel/linux/linux-6.6/drivers/dma/fsl-dpaa2-qdma/
Ddpaa2-qdma.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 u32 rbpcmd; /* Route-by-port command */
36 #define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */
37 #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
38 #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
43 #define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */
51 #define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */
62 #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
63 #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
110 * dpaa2_qdma_priv - driver private data
/kernel/linux/linux-5.10/drivers/dma/fsl-dpaa2-qdma/
Ddpaa2-qdma.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 u32 rbpcmd; /* Route-by-port command */
36 #define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */
37 #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
38 #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
43 #define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */
51 #define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */
62 #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
63 #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
110 * dpaa2_qdma_priv - driver private data
/kernel/linux/linux-6.6/drivers/base/regmap/
Dregcache.c1 // SPDX-License-Identifier: GPL-2.0
32 if (!map->num_reg_defaults_raw) in regcache_hw_init()
33 return -EINVAL; in regcache_hw_init()
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) in regcache_hw_init()
37 if (regmap_readable(map, i * map->reg_stride) && in regcache_hw_init()
38 !regmap_volatile(map, i * map->reg_stride)) in regcache_hw_init()
41 /* all registers are unreadable or volatile, so just bypass */ in regcache_hw_init()
43 map->cache_bypass = true; in regcache_hw_init()
47 map->num_reg_defaults = count; in regcache_hw_init()
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), in regcache_hw_init()
[all …]
/kernel/linux/linux-6.6/drivers/clk/ti/
Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
[all …]
/kernel/linux/linux-5.10/include/linux/clk/
Dti.h18 #include <linux/clk-provider.h>
22 * struct clk_omap_reg - OMAP register declaration
34 * struct dpll_data - DPLL registers and integration data
38 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
48 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
50 * @min_divider: minimum valid non-bypass divider value (actual)
51 * @max_divider: maximum valid non-bypass divider value (actual)
61 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
63 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
69 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/nxp/imx8-isi/
Dimx8-isi-hw.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019-2020 NXP
11 #include "imx8-isi-core.h"
12 #include "imx8-isi-regs.h"
18 return readl(pipe->regs + reg); in mxc_isi_read()
23 writel(val, pipe->regs + reg); in mxc_isi_write()
26 /* -----------------------------------------------------------------------------
33 if (pipe->isi->pdata->has_36bit_dma) in mxc_isi_channel_set_inbuf()
53 if (pipe->isi->pdata->has_36bit_dma) { in mxc_isi_channel_set_outbuf()
69 if (pipe->isi->pdata->has_36bit_dma) { in mxc_isi_channel_set_outbuf()
[all …]
/kernel/linux/linux-5.10/drivers/iommu/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
6 # The IOASID library may also be used by non-IOMMU_API users
37 Enable support for the ARM long descriptor pagetable format.
39 sizes at both stage-1 and stage-2, as well as address spaces
40 up to 48-bits in size.
46 Enable self-tests for LPAE page table allocator. This performs
47 a series of page-table consistency checks during boot.
56 Enable support for the ARM Short-descriptor pagetable format.
57 This supports 32-bit virtual and physical addresses mapped using
[all …]
/kernel/linux/linux-6.6/include/linux/clk/
Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
26 * struct dpll_data - DPLL registers and integration data
30 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
40 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
42 * @min_divider: minimum valid non-bypass divider value (actual)
43 * @max_divider: maximum valid non-bypass divider value (actual)
53 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
55 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 enc10->base.ctx
39 enc10->base.ctx->logger
42 (enc10->link_regs->reg)
46 enc10->link_shift->field_name, enc10->link_mask->field_name
52 * ASIC-dependent, actual values for register programming
98 struct dc_bios *bp = enc10->base.ctx->dc_bios; in link_transmitter_control()
100 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
107 bool enable) in enable_phy_bypass_mode() argument
112 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
41 enc10->base.ctx
43 enc10->base.ctx->logger
46 (enc10->link_regs->reg)
50 enc10->link_shift->field_name, enc10->link_mask->field_name
56 * ASIC-dependent, actual values for register programming
102 struct dc_bios *bp = enc10->base.ctx->dc_bios; in link_transmitter_control()
104 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
111 bool enable) in enable_phy_bypass_mode() argument
116 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 enc110->base.ctx
59 enc110->base.ctx->logger
62 (enc110->link_regs->reg)
65 (enc110->aux_regs->reg)
68 (enc110->hpd_regs->reg)
75 * ASIC-dependent, actual values for register programming
91 (reg + enc110->offsets.dig)
94 (reg + enc110->offsets.dp)
127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
[all …]

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