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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
3 The CGU generates multiple independent clocks for the core and the
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
13 corresponds to one of the base clocks for the LPC18xx.
15 - Above text taken from NXP LPC1850 User Manual.
[all …]
Dexynos5433-clock.txt1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
13 which generates clocks for LLI (Low Latency Interface) IP.
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
[all …]
Dexynos5260-clock.txt1 * Samsung Exynos5260 Clock Controller
3 Exynos5260 has 13 clock controllers which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos5260-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
[all …]
Dmvebu-core-clock.txt1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
[all …]
Dclock-bindings.txt1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
[all …]
Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
[all …]
Dpistachio-clock.txt1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
[all …]
Dexynos7-clock.txt1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
22 Required Properties for Clock Controller:
[all …]
Dvt8500.txt1 Device Tree Clock bindings for arch-vt8500
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
15 Required properties for PLL clocks:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
3 The CGU generates multiple independent clocks for the core and the
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
13 corresponds to one of the base clocks for the LPC18xx.
15 - Above text taken from NXP LPC1850 User Manual.
[all …]
Dmvebu-core-clock.txt1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
[all …]
Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
[all …]
Dpistachio-clock.txt1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
[all …]
Dvt8500.txt1 Device Tree Clock bindings for arch-vt8500
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
15 Required properties for PLL clocks:
[all …]
Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
8 Please refer to the Reference Manual for details.
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
[all …]
/kernel/linux/linux-6.6/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
22 bool "Common Clock Framework"
28 The common clock framework is a single definition of struct
30 implementation of the clock API in include/linux/clk.h.
37 tristate "Clock driver for WM831x/2x PMICs"
46 bool "PLL Driver for HSDK platform"
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
58 Say yes here to build support for Texas Instruments' LMK04832 Ultra
[all …]
/kernel/linux/linux-6.6/drivers/clk/mediatek/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # MediaTek Clock Drivers
5 menu "Clock driver for MediaTek SoC"
12 MediaTek SoCs' clock support.
15 bool "clock driver for MediaTek FHCTL hardware control"
22 bool "Clock driver for MediaTek MT2701"
30 bool "Clock driver for MediaTek MT2701 mmsys"
36 bool "Clock driver for MediaTek MT2701 imgsys"
42 bool "Clock driver for MediaTek MT2701 vdecsys"
48 bool "Clock driver for MediaTek MT2701 hifsys"
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 tristate "Support for Qualcomm's clock controllers"
26 Support for the A53 PLL on MSM8916 devices. It provides
32 tristate "MSM8916 APCS Clock Controller"
35 Support for the APCS Clock Controller on msm8916 devices. The
41 tristate "MSM8996 CPU Clock Controller"
45 Support for the CPU clock controller on msm8996 devices.
46 Say Y if you want to support CPU clock scaling using CPUfreq
47 drivers for dyanmic power management.
50 tristate "RPM based Clock Controller"
[all …]
/kernel/linux/linux-5.10/drivers/clk/mediatek/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # MediaTek Clock Drivers
5 menu "Clock driver for MediaTek SoC"
12 MediaTek SoCs' clock support.
15 bool "Clock driver for MediaTek MT2701"
23 bool "Clock driver for MediaTek MT2701 mmsys"
29 bool "Clock driver for MediaTek MT2701 imgsys"
35 bool "Clock driver for MediaTek MT2701 vdecsys"
41 bool "Clock driver for MediaTek MT2701 hifsys"
47 bool "Clock driver for MediaTek MT2701 ethsys"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/
Dgate.txt1 Binding for Texas Instruments gate clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 is provided for this clock, the code assumes that a clockdomain
9 will be controlled instead and the corresponding hw-ops for
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
14 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
17 - compatible : shall be one of:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/
Dgate.txt1 Binding for Texas Instruments gate clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 is provided for this clock, the code assumes that a clockdomain
9 will be controlled instead and the corresponding hw-ops for
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
14 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
17 - compatible : shall be one of:
[all …]
/kernel/linux/linux-6.6/drivers/clk/qcom/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 tristate "Support for Qualcomm's clock controllers"
26 Support for the A53 PLL on MSM8916 devices. It provides
32 tristate "A7 PLL driver for SDX55 and SDX65"
34 Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
54 Support for the CPU clock controller on msm8996 devices.
55 Say Y if you want to support CPU clock scaling using CPUfreq
[all …]
/kernel/linux/linux-5.10/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
20 Select this option when the clock API in <linux/clk.h> is implemented
26 bool "Common Clock Framework"
33 The common clock framework is a single definition of struct
35 implementation of the clock API in include/linux/clk.h.
42 tristate "Clock driver for WM831x/2x PMICs"
51 bool "PLL Driver for HSDK platform"
59 tristate "Clock driver for Maxim 77620/77686/77802 MFD"
63 clock.
[all …]
/kernel/linux/linux-5.10/sound/soc/qcom/qdsp6/
Dq6afe.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <dt-bindings/sound/qcom,q6afe.h>
26 /* Clock ID for Primary I2S IBIT */
28 /* Clock ID for Primary I2S EBIT */
30 /* Clock ID for Secondary I2S IBIT */
32 /* Clock ID for Secondary I2S EBIT */
34 /* Clock ID for Tertiary I2S IBIT */
36 /* Clock ID for Tertiary I2S EBIT */
38 /* Clock ID for Quartnery I2S IBIT */
40 /* Clock ID for Quartnery I2S EBIT */
[all …]
/kernel/linux/linux-6.6/sound/soc/qcom/qdsp6/
Dq6afe.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <dt-bindings/sound/qcom,q6afe.h>
26 /* Clock ID for Primary I2S IBIT */
28 /* Clock ID for Primary I2S EBIT */
30 /* Clock ID for Secondary I2S IBIT */
32 /* Clock ID for Secondary I2S EBIT */
34 /* Clock ID for Tertiary I2S IBIT */
36 /* Clock ID for Tertiary I2S EBIT */
38 /* Clock ID for Quartnery I2S IBIT */
40 /* Clock ID for Quartnery I2S EBIT */
[all …]

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