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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Darm,coresight-catu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
12 This framework provides a kernel interface for the CoreSight debug
14 a topological view of the CoreSight components based on a DT
19 module will be called coresight.
21 if CORESIGHT
23 tristate "CoreSight Link and Sink drivers"
25 This enables support for CoreSight link and sink drivers that are
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Dcoresight-catu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Coresight Address Translation Unit support
12 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-priv.h"
19 #include "coresight-tmc.h"
22 dev_get_drvdata(csdev->dev.parent)
24 /* Verbose output for CATU table contents */
31 DEFINE_CORESIGHT_DEVLIST(catu_devs, "catu");
39 * CATU uses a page size of 4KB for page tables as well as data pages.
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for CoreSight drivers.
5 obj-$(CONFIG_CORESIGHT) += coresight.o
6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7 coresight-sysfs.o
8 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
9 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
10 coresight-tmc-etr.o
11 obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o
12 obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
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Dcoresight-tmc-etr.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight.h>
9 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-etm-perf.h"
19 #include "coresight-priv.h"
20 #include "coresight-tmc.h"
30 * etr_perf_buffer - Perf buffer used for ETR
31 * @drvdata - The ETR drvdaga this buffer has been allocated for.
32 * @etr_buf - Actual buffer used by the ETR
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Dcoresight-catu.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "coresight-priv.h"
41 * AXI - ARPROT bits:
45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
47 * Bit 2: 0 - Data access, 1 - instruction access.
49 * CATU AXICTRL:ARPROT[2] is res0 as we always access data.
73 return coresight_read_reg_pair(drvdata->base, offset, -1); \
78 coresight_write_reg_pair(drvdata->base, val, offset, -1); \
85 return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \
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Dcoresight-tmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
45 /* TMC_CTL - 0x020 */
47 /* TMC_STS - 0x00C */
53 * TMC_AXICTL - 0x110
55 * TMC AXICTL format for SoC-400
56 * Bits [0-1] : ProtCtrlBit0-1
57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
60 * Bits [8-11] : WrBurstLen
61 * Bits [12-31] : Reserved.
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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
13 This framework provides a kernel interface for the CoreSight debug
15 a topological view of the CoreSight components based on a DT
20 module will be called coresight.
22 if CORESIGHT
24 tristate "CoreSight Link and Sink drivers"
26 This enables support for CoreSight link and sink drivers that are
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Dcoresight-catu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Coresight Address Translation Unit support
12 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-priv.h"
19 #include "coresight-tmc.h"
22 dev_get_drvdata(csdev->dev.parent)
24 /* Verbose output for CATU table contents */
31 DEFINE_CORESIGHT_DEVLIST(catu_devs, "catu");
39 * CATU uses a page size of 4KB for page tables as well as data pages.
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for CoreSight drivers.
5 obj-$(CONFIG_CORESIGHT) += coresight.o
6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7 coresight-sysfs.o coresight-syscfg.o coresight-config.o \
8 coresight-cfg-preload.o coresight-cfg-afdo.o \
9 coresight-syscfg-configfs.o coresight-trace-id.o
10 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
11 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
12 coresight-tmc-etr.o
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Dcoresight-catu.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "coresight-priv.h"
41 * AXI - ARPROT bits:
45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
47 * Bit 2: 0 - Data access, 1 - instruction access.
49 * CATU AXICTRL:ARPROT[2] is res0 as we always access data.
73 return csdev_access_relaxed_read32(&drvdata->csdev->access, offset); \
78 csdev_access_relaxed_write32(&drvdata->csdev->access, val, offset); \
85 return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \
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Dcoresight-tmc-etr.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight.h>
9 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-etm-perf.h"
19 #include "coresight-priv.h"
20 #include "coresight-tmc.h"
30 * etr_perf_buffer - Perf buffer used for ETR
31 * @drvdata - The ETR drvdaga this buffer has been allocated for.
32 * @etr_buf - Actual buffer used by the ETR
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Dcoresight-tmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
45 /* TMC_CTL - 0x020 */
47 /* TMC_STS - 0x00C */
53 * TMC_AXICTL - 0x110
55 * TMC AXICTL format for SoC-400
56 * Bits [0-1] : ProtCtrlBit0-1
57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
60 * Bits [8-11] : WrBurstLen
61 * Bits [12-31] : Reserved.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight.txt1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
8 sink. Each CoreSight component device should use these properties to describe
11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
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/kernel/linux/linux-5.10/drivers/acpi/
Dacpi_amba.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
24 {"ARMHC500", 0}, /* ARM CoreSight ETM4x */
25 {"ARMHC501", 0}, /* ARM CoreSight ETR */
26 {"ARMHC502", 0}, /* ARM CoreSight STM */
27 {"ARMHC503", 0}, /* ARM CoreSight Debug */
28 {"ARMHC979", 0}, /* ARM CoreSight TPIU */
29 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
30 {"ARMHC98D", 0}, /* ARM CoreSight Dynamic Replicator */
31 {"ARMHC9CA", 0}, /* ARM CoreSight CATU */
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/kernel/linux/linux-6.6/drivers/acpi/arm64/
Damba.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
24 {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */
25 {"ARMHC501", 0}, /* ARM CoreSight ETR */
26 {"ARMHC502", 0}, /* ARM CoreSight STM */
27 {"ARMHC503", 0}, /* ARM CoreSight Debug */
28 {"ARMHC979", 0}, /* ARM CoreSight TPIU */
29 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
30 {"ARMHC98D", 0}, /* ARM CoreSight Dynamic Replicator */
31 {"ARMHC9CA", 0}, /* ARM CoreSight CATU */
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